From 71a02c6a4c8f12d2a08074e963ec4e1270433a79 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 27 Oct 2020 20:33:38 +0000 Subject: [PATCH] further investigation note --- 3d_gpu/architecture/compared_to_register_renaming.mdwn | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/3d_gpu/architecture/compared_to_register_renaming.mdwn b/3d_gpu/architecture/compared_to_register_renaming.mdwn index 8b4e2e4c7..15430a7f9 100644 --- a/3d_gpu/architecture/compared_to_register_renaming.mdwn +++ b/3d_gpu/architecture/compared_to_register_renaming.mdwn @@ -12,7 +12,8 @@ are spread out across multiple physical registers. stations. unlike in the Tomasulo Algorithm, they're just not given "names" because Cray and Thornton solved a problem they didn't realise everyone else would have. See [[tomasulo_transformation]] and -) + +However further investigation shows that this may be WaW hazard relate) The following diagrams are assuming that the fetch, decode, branch prediction, and register renaming can handle 4 instructions per clock -- 2.30.2