From 71a70da437332fa0a26a6d7d05cfa7577d7e6b5f Mon Sep 17 00:00:00 2001 From: whitequark Date: Sat, 26 Jan 2019 15:29:09 +0000 Subject: [PATCH] test.compat: reenable tests converting to Verilog. --- nmigen/compat/fhdl/verilog.py | 2 +- nmigen/test/compat/support.py | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/nmigen/compat/fhdl/verilog.py b/nmigen/compat/fhdl/verilog.py index bced762..ad2f588 100644 --- a/nmigen/compat/fhdl/verilog.py +++ b/nmigen/compat/fhdl/verilog.py @@ -1,6 +1,6 @@ import warnings -from ...hdl import Fragment +from ...hdl.ir import Fragment from ...back import verilog from .conv_output import ConvOutput diff --git a/nmigen/test/compat/support.py b/nmigen/test/compat/support.py index 2a1292f..3de3276 100644 --- a/nmigen/test/compat/support.py +++ b/nmigen/test/compat/support.py @@ -1,13 +1,13 @@ from ...compat import * -# from ...compat.fhdl import verilog +from ...compat.fhdl import verilog class SimCase: def setUp(self, *args, **kwargs): self.tb = self.TestBench(*args, **kwargs) - # def test_to_verilog(self): - # verilog.convert(self.tb) + def test_to_verilog(self): + verilog.convert(self.tb) def run_with(self, generator): run_simulation(self.tb, generator) -- 2.30.2