From 71b89e4c46e5487e995f6de6f2d1cb478479264c Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 30 Jun 2013 14:32:47 +0200 Subject: [PATCH] fhdl/verilog: lower complex slices before reset insertion --- migen/fhdl/verilog.py | 1 + 1 file changed, 1 insertion(+) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index d9683e94..7a6f7ce6 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -302,6 +302,7 @@ def convert(f, ios=None, name="top", else: raise KeyError("Unresolved clock domain: '"+cd_name+"'") + f = lower_complex_slices(f) _insert_resets(f) f = lower_basics(f) fs, lowered_specials = _lower_specials(special_overrides, f.specials) -- 2.30.2