From 71bed3ed83889bcbdb52ca15ac57a76d2461aec5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 5 Sep 2020 20:52:35 +0100 Subject: [PATCH] hmmm XICS data being asserted on wb bus for too long --- src/soc/interrupts/xics.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/soc/interrupts/xics.py b/src/soc/interrupts/xics.py index 23e96647..a0a852d3 100644 --- a/src/soc/interrupts/xics.py +++ b/src/soc/interrupts/xics.py @@ -93,8 +93,9 @@ class XICS_ICP(Elaboratable): # We delay core_irq_out by a cycle to help with timing sync += self.core_irq_o.eq(r.irq) - comb += self.bus.dat_r.eq(r.wb_rd_data) - comb += self.bus.ack.eq(r.wb_ack) + comb += self.bus.ack.eq(r.wb_ack & self.bus.cyc) + with m.If(self.bus.ack): + comb += self.bus.dat_r.eq(r.wb_rd_data) v = RegInternal() xirr_accept_rd = Signal() -- 2.30.2