From 71cd946ea908ee35274b311e5cefe0e2c55befe2 Mon Sep 17 00:00:00 2001 From: Dmitry Selyutin Date: Mon, 29 May 2023 01:04:57 +0300 Subject: [PATCH] ppc: support minmax instruction --- gas/testsuite/gas/ppc/minmax.d | 16 ++++++++++++++++ gas/testsuite/gas/ppc/minmax.s | 8 ++++++++ gas/testsuite/gas/ppc/ppc.exp | 1 + opcodes/ppc-opc.c | 20 ++++++++++++++++++-- 4 files changed, 43 insertions(+), 2 deletions(-) create mode 100644 gas/testsuite/gas/ppc/minmax.d create mode 100644 gas/testsuite/gas/ppc/minmax.s diff --git a/gas/testsuite/gas/ppc/minmax.d b/gas/testsuite/gas/ppc/minmax.d new file mode 100644 index 00000000000..24146d2eea0 --- /dev/null +++ b/gas/testsuite/gas/ppc/minmax.d @@ -0,0 +1,16 @@ +#as: -mlibresoc +#objdump: -dr -Mlibresoc + +.*: file format .* + + +Disassembly of section \.text: +0+ <\.text>: +.*:\s+(4f e0 00 06|06 00 e0 4f)\s+minmax\s+r31,r0,r0,0 +.*:\s+(4c 1f 00 06|06 00 1f 4c)\s+minmax\s+r0,r31,r0,0 +.*:\s+(4c 00 f8 06|06 f8 00 4c)\s+minmax\s+r0,r0,r31,0 +.*:\s+(4c 00 07 06|06 07 00 4c)\s+minmax\s+r0,r0,r0,7 +.*:\s+(4f e0 00 07|07 00 e0 4f)\s+minmax.\s+r31,r0,r0,0 +.*:\s+(4c 1f 00 07|07 00 1f 4c)\s+minmax.\s+r0,r31,r0,0 +.*:\s+(4c 00 f8 07|07 f8 00 4c)\s+minmax.\s+r0,r0,r31,0 +.*:\s+(4c 00 07 07|07 07 00 4c)\s+minmax.\s+r0,r0,r0,7 diff --git a/gas/testsuite/gas/ppc/minmax.s b/gas/testsuite/gas/ppc/minmax.s new file mode 100644 index 00000000000..211a317e3d4 --- /dev/null +++ b/gas/testsuite/gas/ppc/minmax.s @@ -0,0 +1,8 @@ +minmax 31,0,0,0 +minmax 0,31,0,0 +minmax 0,0,31,0 +minmax 0,0,0,7 +minmax. 31,0,0,0 +minmax. 0,31,0,0 +minmax. 0,0,31,0 +minmax. 0,0,0,7 diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp index 549e1415872..1a8a2bb263e 100644 --- a/gas/testsuite/gas/ppc/ppc.exp +++ b/gas/testsuite/gas/ppc/ppc.exp @@ -174,3 +174,4 @@ run_dump_test "sadd" run_dump_test "dsld" run_dump_test "dsrd" run_dump_test "maddedus" +run_dump_test "minmax" diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index a88e483866f..aa7fe549357 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -4034,6 +4034,12 @@ const struct powerpc_operand powerpc_operands[] = #define LBM2 SVo + 1 { 0x1, 5, NULL, NULL, 0 }, + +#define FMM LBM2 + 1 + { 0xf, 7, NULL, NULL, 0 }, + +#define MMM FMM + 1 + { 0x7, 8, NULL, NULL, 0 }, }; const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands); @@ -4964,6 +4970,13 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands); | (((uint64_t)(rc)) & 1)) #define VA2_MASK VA2 (0x3f, 0x1f, 0x1) +/* An MM form instruction. */ +#define MM(op, xop, rc) \ + (OP (op) \ + | ((((uint64_t)(xop)) & 0x3f) << 1) \ + | (((uint64_t)(rc)) & 1)) +#define MM_MASK MM (0x3f, 0x3f, 0x1) + /* The BO encodings used in extended conditional branch mnemonics. */ #define BODNZF (0x0) #define BODNZFP (0x1) @@ -6456,6 +6469,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}}, {"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE|EXT, {RT, NDXD}}, +{"minmax", MM(19,3,0), MM_MASK, SFFS, PPCVLE, {RT, RA, RB, MMM}}, +{"minmax.", MM(19,3,1), MM_MASK, SFFS, PPCVLE, {RT, RA, RB, MMM}}, + {"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BH}}, {"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BH}}, {"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE|EXT, {BH}}, @@ -7066,8 +7082,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"sadduw", ZRC(22,238,0), Z2_MASK, SFFS, PPCVLE, {RT, RA, RB, SHP1}}, {"sadduw.", ZRC(22,238,1), Z2_MASK, SFFS, PPCVLE, {RT, RA, RB, SHP1}}, -{"cprop", XRC(22,398,0), X_MASK, SVP64, PPCVLE, {RT, RA, RB}}, -{"cprop.", XRC(22,398,1), X_MASK, SVP64, PPCVLE, {RT, RA, RB}}, +{"cprop", XRC(22,398,0), X_MASK, SFFS, PPCVLE, {RT, RA, RB}}, +{"cprop.", XRC(22,398,1), X_MASK, SFFS, PPCVLE, {RT, RA, RB}}, {"absdacs", XRC(22,502,0), X_MASK, SFFS, PPCVLE, {RT, RA, RB}}, {"absdacs.", XRC(22,502,1), X_MASK, SFFS, PPCVLE, {RT, RA, RB}}, -- 2.30.2