From 71d355560e718147ac9ab769363c6a2b069fd209 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 5 Sep 2019 17:20:29 +0200 Subject: [PATCH] Update README.md Signed-off-by: Clifford Wolf --- README.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index a39737c08..894b152ce 100644 --- a/README.md +++ b/README.md @@ -333,7 +333,8 @@ Verilog Attributes and non-standard features is run in ``-pwires`` mode). - Wires marked with the ``hierconn`` attribute are connected to wires with the - same name when they are imported from sub-modules by ``flatten``. + same name (format ``cell_name.identifier``) when they are imported from + sub-modules by ``flatten``. - The ``clkbuf_driver`` attribute can be set on an output port of a blackbox module to mark it as a clock buffer output, and thus prevent ``clkbufmap`` -- 2.30.2