From 71dd52e0560e3d32dd040301ae99e0ae2da4384e Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Sat, 30 Nov 2019 13:24:46 -0500 Subject: [PATCH] panfrost: Remove blend shader hack This is no longer used. Signed-off-by: Alyssa Rosenzweig --- src/gallium/drivers/panfrost/pan_blend_shaders.c | 3 --- src/panfrost/include/panfrost-job.h | 3 +-- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/src/gallium/drivers/panfrost/pan_blend_shaders.c b/src/gallium/drivers/panfrost/pan_blend_shaders.c index 33a1f61c941..5d7eb9573eb 100644 --- a/src/gallium/drivers/panfrost/pan_blend_shaders.c +++ b/src/gallium/drivers/panfrost/pan_blend_shaders.c @@ -175,9 +175,6 @@ panfrost_compile_blend_shader( midgard_program program; midgard_compile_shader_nir(shader, &program, true, screen->gpu_id); - /* At least two work registers are needed due to an encoding quirk */ - res.work_count = MAX2(program.work_register_count, 2); - /* Allow us to patch later */ res.patch_index = program.blend_patch_offset; res.first_tag = program.first_tag; diff --git a/src/panfrost/include/panfrost-job.h b/src/panfrost/include/panfrost-job.h index ff0d9aa9036..796be2372ac 100644 --- a/src/panfrost/include/panfrost-job.h +++ b/src/panfrost/include/panfrost-job.h @@ -436,8 +436,7 @@ union midgard_blend { struct midgard_blend_rt { /* Flags base value of 0x200 to enable the render target. * OR with 0x1 for blending (anything other than REPLACE). - * OR with 0x2 for programmable blending with 0-2 registers - * OR with 0x3 for programmable blending with 2+ registers + * OR with 0x2 for programmable blending * OR with MALI_BLEND_SRGB for implicit sRGB */ -- 2.30.2