From 71f2389b8d2acd164b484b34ede7037a6a882655 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Tue, 4 Oct 2022 13:11:51 +0100
Subject: [PATCH]

---
 openpower/sv/svp64/discussion.mdwn | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/openpower/sv/svp64/discussion.mdwn b/openpower/sv/svp64/discussion.mdwn
index 6b367e1be..db96851bc 100644
--- a/openpower/sv/svp64/discussion.mdwn
+++ b/openpower/sv/svp64/discussion.mdwn
@@ -227,7 +227,8 @@ Summary so far:
 * failfirst needs to be an illegal exception if all-scalar
 * non-zeroing predication on all-scalar with VL>1 requires
   all relevant bits to be set, this changes to the **first**
-  bit for auto-VL=1
+  bit for auto-VL=1.  requires an extra reduction instruction.
+* sv.branches should not be touched. at all.
 
 ## answers to 2, RM Modes
 
-- 
2.30.2