From 71fe13914900774601446722853c2e701dad82de Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 27 Jul 2018 11:32:56 +0100 Subject: [PATCH] pep8 cleanup --- src/bsv/interface_decl.py | 16 ++++++++++------ src/bsv/peripheral_gen/base.py | 4 +++- src/bsv/peripheral_gen/flexbus.py | 26 +++++++++++++------------- src/spec/i_class.py | 2 +- 4 files changed, 27 insertions(+), 21 deletions(-) diff --git a/src/bsv/interface_decl.py b/src/bsv/interface_decl.py index 78e774c..55faece 100644 --- a/src/bsv/interface_decl.py +++ b/src/bsv/interface_decl.py @@ -242,7 +242,6 @@ class InterfaceFmt(object): return '\n' + res + '\n' - class Interface(PeripheralIface, InterfaceFmt): """ create an interface from a list of pinspecs. each pinspec is a dictionary, see Pin class arguments @@ -443,7 +442,7 @@ class InterfaceBus(InterfaceFmt): self.buspins = filter(lambda x: x.name_.startswith(self.fbus), self.pins_) self.nonbuspins = filter(lambda x: not x.name_.startswith(self.fbus), - self.pins_) + self.pins_) def get_nonbuspins(self): return self.nonbuspins @@ -538,23 +537,25 @@ class InterfaceLCD(InterfaceBus, Interface): InterfaceBus.__init__(self, self.pins, False, ['data_out', None, None], "Bit#({0})", "out") + class InterfaceFlexBus(InterfaceMultiBus, Interface): def __init__(self, ifacename, pinspecs, ganged=None, single=False): Interface.__init__(self, ifacename, pinspecs, ganged, single) InterfaceMultiBus.__init__(self, self.pins) self.add_bus(True, ['ad_out', 'ad_out_en', 'ad_in'], - "Bit#({0})", "ad") + "Bit#({0})", "ad") self.add_bus(False, ['bwe', None, None], - "Bit#({0})", "bwe") + "Bit#({0})", "bwe") self.add_bus(False, ['tsiz', None, None], - "Bit#({0})", "tsiz") + "Bit#({0})", "tsiz") self.add_bus(False, ['cs', None, None], - "Bit#({0})", "cs") + "Bit#({0})", "cs") def ifacedef2(self, *args): return InterfaceMultiBus.ifacedef2(self, *args) + class InterfaceSD(InterfaceBus, Interface): def __init__(self, *args): @@ -562,6 +563,7 @@ class InterfaceSD(InterfaceBus, Interface): InterfaceBus.__init__(self, self.pins, True, ['out', 'out_en', 'in'], "Bit#({0})", "d") + class InterfaceNSPI(InterfaceBus, Interface): def __init__(self, *args): @@ -570,6 +572,7 @@ class InterfaceNSPI(InterfaceBus, Interface): ['io_out', 'io_out_en', 'io_in'], "Bit#({0})", "io") + class InterfaceEINT(Interface): """ uses old-style (non-get/put) for now """ @@ -592,6 +595,7 @@ class InterfaceGPIO(InterfaceBus, Interface): InterfaceBus.__init__(self, self.pins, True, ['out', 'out_en', 'in'], "Vector#({0},Bit#(1))", ifacename[-1]) + class Interfaces(InterfacesBase, PeripheralInterfaces): """ contains a list of interface definitions """ diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py index c88080d..c9c53ef 100644 --- a/src/bsv/peripheral_gen/base.py +++ b/src/bsv/peripheral_gen/base.py @@ -178,7 +178,9 @@ else""" n_ = "{0}{1}".format(n, count) n_ = '{0}.{1}'.format(n_, fname) n_ = self.ifname_tweak(pname, 'in', n_) - ret.append("mkConnection({1},\n\t\t\t{0});".format(ps_, n_)) + ret.append( + "mkConnection({1},\n\t\t\t{0});".format( + ps_, n_)) return '\n'.join(ret) def mk_cellconn(self, *args): diff --git a/src/bsv/peripheral_gen/flexbus.py b/src/bsv/peripheral_gen/flexbus.py index 8fed547..7302d46 100644 --- a/src/bsv/peripheral_gen/flexbus.py +++ b/src/bsv/peripheral_gen/flexbus.py @@ -7,7 +7,7 @@ class flexbus(PBase): return "import FlexBus_Types::*;" def num_axi_regs32(self): - return 0x4000000 # defines an entire memory range + return 0x4000000 # defines an entire memory range def extfastifinstance(self, name, count): return self._extifinstance(name, count, "_out", "", True, @@ -26,13 +26,13 @@ class flexbus(PBase): def pinname_in(self, pname): return {'ta': 'flexbus_side.tAn', - }.get(pname, '') + }.get(pname, '') def pinname_out(self, pname): return {'ale': 'flexbus_side.m_ALE', - 'oe' : 'flexbus_side.m_OEn', - 'rw' : 'flexbus_side.m_R_Wn', - }.get(pname, '') + 'oe': 'flexbus_side.m_OEn', + 'rw': 'flexbus_side.m_R_Wn', + }.get(pname, '') def mk_pincon(self, name, count): ret = [PBase.mk_pincon(self, name, count)] @@ -44,13 +44,13 @@ class flexbus(PBase): ps = "pinmux.peripheral_side.%s" % sname n = "{0}".format(name) for stype, ptype in [ - ('cs', 'm_FBCSn'), - ('bwe', 'm_BWEn'), - ('tbst', 'm_TBSTn'), - ('tsiz', 'm_TSIZ'), - ('ad_in', 'm_AD'), - ('ad_out', 'm_din'), - ('ad_en', 'm_OE32n'), - ]: + ('cs', 'm_FBCSn'), + ('bwe', 'm_BWEn'), + ('tbst', 'm_TBSTn'), + ('tsiz', 'm_TSIZ'), + ('ad_in', 'm_AD'), + ('ad_out', 'm_din'), + ('ad_en', 'm_OE32n'), + ]: ret.append(template.format(ps, ptype, n, stype)) return '\n'.join(ret) diff --git a/src/spec/i_class.py b/src/spec/i_class.py index 11a57b5..6401538 100644 --- a/src/spec/i_class.py +++ b/src/spec/i_class.py @@ -60,7 +60,7 @@ def pinspec(): } ps = PinSpec(pinbanks, fixedpins, function_names, - ['lcd', 'jtag', 'fb' ]) + ['lcd', 'jtag', 'fb']) # Bank A, 0-27 ps.gpio("", ('A', 0), 0, 0, 28) -- 2.30.2