From 7239b19cc512477017cc385d78fcc887032537d0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 21 Mar 2021 13:17:26 +0000 Subject: [PATCH] naah. back to "sv." syntax for SVP64 assembly --- src/soc/decoder/isa/test_caller_setvl.py | 2 +- src/soc/decoder/isa/test_caller_svp64.py | 14 ++++----- .../isa/test_caller_svp64_predication.py | 20 ++++++------- src/soc/fu/alu/test/svp64_cases.py | 18 +++++------ src/soc/sv/trans/svp64.py | 30 +++++++++---------- 5 files changed, 42 insertions(+), 42 deletions(-) diff --git a/src/soc/decoder/isa/test_caller_setvl.py b/src/soc/decoder/isa/test_caller_setvl.py index cb215635..ad7991f1 100644 --- a/src/soc/decoder/isa/test_caller_setvl.py +++ b/src/soc/decoder/isa/test_caller_setvl.py @@ -49,7 +49,7 @@ class DecoderTestCase(FHDLTestCase): # 1 = 5 + 9 => 0x5555 = 0x4321+0x1234 # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 isa = SVP64Asm(["setvl 3, 0, 1, 1, 1", - 'svadd 1.v, 5.v, 9.v' + 'sv.add 1.v, 5.v, 9.v' ]) lst = list(isa) print ("listing", lst) diff --git a/src/soc/decoder/isa/test_caller_svp64.py b/src/soc/decoder/isa/test_caller_svp64.py index 44e71049..7875dc08 100644 --- a/src/soc/decoder/isa/test_caller_svp64.py +++ b/src/soc/decoder/isa/test_caller_svp64.py @@ -26,8 +26,8 @@ class DecoderTestCase(FHDLTestCase): "addi 2, 0, 0x0008", "addi 5, 0, 0x1234", "addi 6, 0, 0x1235", - "svstw 5.v, 0(1.v)", - "svlwz 9.v, 0(1.v)"]) + "sv.stw 5.v, 0(1.v)", + "sv.lwz 9.v, 0(1.v)"]) lst = list(lst) # SVSTATE (in this case, VL=2) @@ -46,7 +46,7 @@ class DecoderTestCase(FHDLTestCase): # adds: # 1 = 5 + 9 => 0x5555 = 0x4321+0x1234 # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 - isa = SVP64Asm(['svadd 1.v, 5.v, 9.v' + isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v' ]) lst = list(isa) print ("listing", lst) @@ -75,7 +75,7 @@ class DecoderTestCase(FHDLTestCase): # adds: # 1 = 5 + 9 => 0x5555 = 0x4321+0x1234 # r1 is scalar so ENDS EARLY - isa = SVP64Asm(['svadd 1, 5.v, 9.v' + isa = SVP64Asm(['sv.add 1, 5.v, 9.v' ]) lst = list(isa) print ("listing", lst) @@ -103,7 +103,7 @@ class DecoderTestCase(FHDLTestCase): # adds: # 1 = 5 + 9 => 0x5555 = 0x4321+0x1234 # 2 = 5 + 10 => 0x5432 = 0x4321+0x1111 - isa = SVP64Asm(['svadd 1.v, 5, 9.v' + isa = SVP64Asm(['sv.add 1.v, 5, 9.v' ]) lst = list(isa) print ("listing", lst) @@ -131,7 +131,7 @@ class DecoderTestCase(FHDLTestCase): def test_sv_add_vl_0(self): # adds: # none because VL is zer0 - isa = SVP64Asm(['svadd 1, 5.v, 9.v' + isa = SVP64Asm(['sv.add 1, 5.v, 9.v' ]) lst = list(isa) print ("listing", lst) @@ -158,7 +158,7 @@ class DecoderTestCase(FHDLTestCase): # adds when Rc=1: TODO CRs higher up # 1 = 5 + 9 => 0 = -1+1 CR0=0b100 # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 CR1=0b010 - isa = SVP64Asm(['svadd. 1.v, 5.v, 9.v' + isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v' ]) lst = list(isa) print ("listing", lst) diff --git a/src/soc/decoder/isa/test_caller_svp64_predication.py b/src/soc/decoder/isa/test_caller_svp64_predication.py index 999ee702..837c42d8 100644 --- a/src/soc/decoder/isa/test_caller_svp64_predication.py +++ b/src/soc/decoder/isa/test_caller_svp64_predication.py @@ -26,8 +26,8 @@ class DecoderTestCase(FHDLTestCase): "addi 2, 0, 0x0008", "addi 5, 0, 0x1234", "addi 6, 0, 0x1235", - "svstw 5.v, 0(1.v)", - "svlwz 9.v, 0(1.v)"]) + "sv.stw 5.v, 0(1.v)", + "sv.lwz 9.v, 0(1.v)"]) lst = list(lst) # SVSTATE (in this case, VL=2) @@ -64,7 +64,7 @@ class DecoderTestCase(FHDLTestCase): # | # dest r3=0b10 N Y - isa = SVP64Asm(['svextsb/sm=~r3/m=r3 5.v, 9.v' + isa = SVP64Asm(['sv.extsb/sm=~r3/m=r3 5.v, 9.v' ]) lst = list(isa) print ("listing", lst) @@ -90,7 +90,7 @@ class DecoderTestCase(FHDLTestCase): def test_sv_extsw_intpred_dz(self): # extsb, integer twin-pred mask: dest is r3 (0b01), zeroing on dest - isa = SVP64Asm(['svextsb/m=r3/dz 5.v, 9.v' + isa = SVP64Asm(['sv.extsb/m=r3/dz 5.v, 9.v' ]) lst = list(isa) print ("listing", lst) @@ -120,7 +120,7 @@ class DecoderTestCase(FHDLTestCase): # adds, integer predicated mask r3=0b10 # 1 = 5 + 9 => not to be touched (skipped) # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 - isa = SVP64Asm(['svadd/m=r3 1.v, 5.v, 9.v' + isa = SVP64Asm(['sv.add/m=r3 1.v, 5.v, 9.v' ]) lst = list(isa) print ("listing", lst) @@ -151,7 +151,7 @@ class DecoderTestCase(FHDLTestCase): # adds, CR predicated mask CR4.eq = 1, CR5.eq = 0, invert (ne) # 1 = 5 + 9 => not to be touched (skipped) # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 - isa = SVP64Asm(['svadd/m=ne 1.v, 5.v, 9.v' + isa = SVP64Asm(['sv.add/m=ne 1.v, 5.v, 9.v' ]) lst = list(isa) print ("listing", lst) @@ -185,7 +185,7 @@ class DecoderTestCase(FHDLTestCase): # adds: # 1 = 5 + 9 => 0x5555 = 0x4321+0x1234 # r1 is scalar so ENDS EARLY - isa = SVP64Asm(['svadd 1, 5.v, 9.v' + isa = SVP64Asm(['sv.add 1, 5.v, 9.v' ]) lst = list(isa) print ("listing", lst) @@ -213,7 +213,7 @@ class DecoderTestCase(FHDLTestCase): # adds: # 1 = 5 + 9 => 0x5555 = 0x4321+0x1234 # 2 = 5 + 10 => 0x5432 = 0x4321+0x1111 - isa = SVP64Asm(['svadd 1.v, 5, 9.v' + isa = SVP64Asm(['sv.add 1.v, 5, 9.v' ]) lst = list(isa) print ("listing", lst) @@ -241,7 +241,7 @@ class DecoderTestCase(FHDLTestCase): def tst_sv_add_vl_0(self): # adds: # none because VL is zer0 - isa = SVP64Asm(['svadd 1, 5.v, 9.v' + isa = SVP64Asm(['sv.add 1, 5.v, 9.v' ]) lst = list(isa) print ("listing", lst) @@ -268,7 +268,7 @@ class DecoderTestCase(FHDLTestCase): # adds when Rc=1: TODO CRs higher up # 1 = 5 + 9 => 0 = -1+1 CR0=0b100 # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 CR1=0b010 - isa = SVP64Asm(['svadd. 1.v, 5.v, 9.v' + isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v' ]) lst = list(isa) print ("listing", lst) diff --git a/src/soc/fu/alu/test/svp64_cases.py b/src/soc/fu/alu/test/svp64_cases.py index 8320036d..4ae5e8ae 100644 --- a/src/soc/fu/alu/test/svp64_cases.py +++ b/src/soc/fu/alu/test/svp64_cases.py @@ -11,7 +11,7 @@ class SVP64ALUTestCase(TestAccumulatorBase): # adds: # 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234 # 2 = 6 + 10 => 0x3334 = 0x2223 + 0x1111 - isa = SVP64Asm(['svadd 1.v, 5.v, 9.v']) + isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v']) lst = list(isa) print("listing", lst) @@ -33,7 +33,7 @@ class SVP64ALUTestCase(TestAccumulatorBase): def case_2_sv_add_scalar(self): # adds: # 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234 - isa = SVP64Asm(['svadd 1, 5, 9']) + isa = SVP64Asm(['sv.add 1, 5, 9']) lst = list(isa) print("listing", lst) @@ -58,7 +58,7 @@ class SVP64ALUTestCase(TestAccumulatorBase): def case_3_sv_check_extra(self): # adds: # 13 = 10 + 7 => 0x4242 = 0x1230 + 0x3012 - isa = SVP64Asm(['svadd 13.v, 10.v, 7.v']) + isa = SVP64Asm(['sv.add 13.v, 10.v, 7.v']) lst = list(isa) print("listing", lst) @@ -80,7 +80,7 @@ class SVP64ALUTestCase(TestAccumulatorBase): # 1 = 5 + 9 => 0 = -1+1 CR0=0b100 # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 CR1=0b010 - isa = SVP64Asm(['svadd. 1.v, 5.v, 9.v']) + isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v']) lst = list(isa) print("listing", lst) @@ -104,7 +104,7 @@ class SVP64ALUTestCase(TestAccumulatorBase): # adds: # 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234 isa = SVP64Asm([ - 'svadd 13.v, 10.v, 7.v', # skipped, because VL == 0 + 'sv.add 13.v, 10.v, 7.v', # skipped, because VL == 0 'add 1, 5, 9' ]) lst = list(isa) @@ -135,8 +135,8 @@ class SVP64ALUTestCase(TestAccumulatorBase): # 14 = 11 + 8 => 0x3012 = 0x3012 + 0x0000 # 15 = 12 + 9 => 0x1234 = 0x0000 + 0x1234 isa = SVP64Asm([ - 'svadd 1.v, 5.v, 9.v', - 'svadd 13.v, 10.v, 7.v' + 'sv.add 1.v, 5.v, 9.v', + 'sv.add 13.v, 10.v, 7.v' ]) lst = list(isa) print("listing", lst) @@ -162,7 +162,7 @@ class SVP64ALUTestCase(TestAccumulatorBase): # adds: # 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234 # r1 is scalar so ENDS EARLY - isa = SVP64Asm(['svadd 1, 5.v, 9.v']) + isa = SVP64Asm(['sv.add 1, 5.v, 9.v']) lst = list(isa) print("listing", lst) @@ -184,7 +184,7 @@ class SVP64ALUTestCase(TestAccumulatorBase): # adds: # 1 = 5 + 9 => 0x5555 = 0x4321+0x1234 # 2 = 5 + 10 => 0x5432 = 0x4321+0x1111 - isa = SVP64Asm(['svadd 1.v, 5, 9.v']) + isa = SVP64Asm(['sv.add 1.v, 5, 9.v']) lst = list(isa) print("listing", lst) diff --git a/src/soc/sv/trans/svp64.py b/src/soc/sv/trans/svp64.py index 18987e86..90019124 100644 --- a/src/soc/sv/trans/svp64.py +++ b/src/soc/sv/trans/svp64.py @@ -180,10 +180,10 @@ class SVP64Asm: continue # identify if is a svp64 mnemonic - if not opcode.startswith('sv'): + if not opcode.startswith('sv.'): yield insn # unaltered continue - opcode = opcode[2:] # strip leading "sv" + opcode = opcode[3:] # strip leading "sv" # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode opmodes = opcode.split("/") # split at "/" @@ -617,21 +617,21 @@ class SVP64Asm: if __name__ == '__main__': lst = ['slw 3, 1, 4', 'extsw 5, 3', - 'svextsw 5, 3', - 'svcmpi 5, 1, 3, 2', - 'svsetb 5, 31', - 'svisel 64.v, 3, 2, 65.v', - 'svsetb/m=r3/sm=1<