From 725be4e207d511afb2df873578c76ce181671dbc Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 5 May 2022 14:32:05 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index fabbb1214..04e6a411e 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -1,3 +1,15 @@ [[!tag whitepapers]] # Why in the 2020s would you invent a new Vector ISA + +Inventing a new Scalar ISA from scratch is over a decade-long task including +simulators and compilers: OpenRISC 1200 took 12 years to mature. +A Vector or SIMD ISA to reach stable +general-purpose auto-vectorisation compiler support has never been +achieved in the history of computing, not with the combined resources of +ARM, Intel, AMD, MIPS, Sun Microsystems, SGI, Cray, and many more. +GPUs have ultra-specialist compilers, and standards managed by the +Khronos Group, with multi-man-century development committment. + +Therefore it begs the question, why on earth would anyone consider this +task? -- 2.30.2