From 7275afd39b4ce6d6a2fccbfe101c38d318f0caf5 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Sat, 9 May 2020 10:51:44 -0400 Subject: [PATCH] Add shift test to test_caller, fix fixedshift being weird on 32 bit shifts --- src/soc/decoder/isa/fixedshift.patch | 96 ++++++++++++++++++++++++++++ src/soc/decoder/isa/test_caller.py | 9 +++ 2 files changed, 105 insertions(+) create mode 100644 src/soc/decoder/isa/fixedshift.patch diff --git a/src/soc/decoder/isa/fixedshift.patch b/src/soc/decoder/isa/fixedshift.patch new file mode 100644 index 00000000..97f55693 --- /dev/null +++ b/src/soc/decoder/isa/fixedshift.patch @@ -0,0 +1,96 @@ +--- fixedshift.py.orig 2020-05-09 09:56:10.393656481 -0400 ++++ fixedshift.py 2020-05-09 10:51:18.674826544 -0400 +@@ -168,9 +168,9 @@ + @inject() + def op_slw(self, RB, RS): + n = RB[59:64] +- r = ROTL32(RS[32:64], n) ++ r = ROTL32(RS[32:64], n.value) + if eq(RB[58], 0): +- m = MASK(32, 63 - n) ++ m = MASK(32, 63 - n.value) + else: + m = concat(0, repeat=64) + RA = r & m +@@ -179,9 +179,9 @@ + @inject() + def op_slw_(self, RB, RS): + n = RB[59:64] +- r = ROTL32(RS[32:64], n) ++ r = ROTL32(RS[32:64], n.value) + if eq(RB[58], 0): +- m = MASK(32, 63 - n) ++ m = MASK(32, 63 - n.value) + else: + m = concat(0, repeat=64) + RA = r & m +@@ -190,9 +190,9 @@ + @inject() + def op_srw(self, RB, RS): + n = RB[59:64] +- r = ROTL32(RS[32:64], 64 - n) ++ r = ROTL32(RS[32:64], 64 - n.value) + if eq(RB[58], 0): +- m = MASK(n + 32, 63) ++ m = MASK(n.value + 32, 63) + else: + m = concat(0, repeat=64) + RA = r & m +@@ -201,9 +201,9 @@ + @inject() + def op_srw_(self, RB, RS): + n = RB[59:64] +- r = ROTL32(RS[32:64], 64 - n) ++ r = ROTL32(RS[32:64], 64 - n.value) + if eq(RB[58], 0): +- m = MASK(n + 32, 63) ++ m = MASK(n.value + 32, 63) + else: + m = concat(0, repeat=64) + RA = r & m +@@ -212,8 +212,8 @@ + @inject() + def op_srawi(self, RS): + n = SH +- r = ROTL32(RS[32:64], 64 - n) +- m = MASK(n + 32, 63) ++ r = ROTL32(RS[32:64], 64 - n.value) ++ m = MASK(n.value + 32, 63) + s = RS[32] + RA = r & m | concat(s, repeat=64) & ~m + carry = s & ne((r & ~m)[32:64], 0) +@@ -224,8 +224,8 @@ + @inject() + def op_srawi_(self, RS): + n = SH +- r = ROTL32(RS[32:64], 64 - n) +- m = MASK(n + 32, 63) ++ r = ROTL32(RS[32:64], 64 - n.value) ++ m = MASK(n.value + 32, 63) + s = RS[32] + RA = r & m | concat(s, repeat=64) & ~m + carry = s & ne((r & ~m)[32:64], 0) +@@ -236,9 +236,9 @@ + @inject() + def op_sraw(self, RB, RS): + n = RB[59:64] +- r = ROTL32(RS[32:64], 64 - n) ++ r = ROTL32(RS[32:64], 64 - n.value) + if eq(RB[58], 0): +- m = MASK(n + 32, 63) ++ m = MASK(n.value + 32, 63) + else: + m = concat(0, repeat=64) + s = RS[32] +@@ -251,9 +251,9 @@ + @inject() + def op_sraw_(self, RB, RS): + n = RB[59:64] +- r = ROTL32(RS[32:64], 64 - n) ++ r = ROTL32(RS[32:64], 64 - n.value) + if eq(RB[58], 0): +- m = MASK(n + 32, 63) ++ m = MASK(n.value + 32, 63) + else: + m = concat(0, repeat=64) + s = RS[32] diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py index 97499d49..467d6d21 100644 --- a/src/soc/decoder/isa/test_caller.py +++ b/src/soc/decoder/isa/test_caller.py @@ -187,6 +187,15 @@ class DecoderTestCase(FHDLTestCase): sim = self.run_tst_program(program) self.assertEqual(sim.gpr(3), SelectableInt(0x20000000, 64)) + def test_shift(self): + lst = ["slw 1, 3, 2"] + initial_regs = [0] * 32 + initial_regs[3] = 0xdeadbeefcafebabe + initial_regs[2] = 5 + with Program(lst) as program: + sim = self.run_tst_program(program, initial_regs) + self.assertEqual(sim.gpr(1), SelectableInt(0x5fd757c0, 32)) + def test_mtcrf(self): for i in range(4): # 0x76540000 gives expected (3+4) (2+4) (1+4) (0+4) for -- 2.30.2