From 7280dbfffe4471be4b764fc0bb75bcbebf132615 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 8 Jul 2020 20:49:32 +0100 Subject: [PATCH] resolving bigendian/littleendian modes in qemu sim --- src/soc/simple/test/test_issuer.py | 12 ++++++------ src/soc/simulator/program.py | 2 +- src/soc/simulator/qemu.py | 14 +++++++++++--- src/soc/simulator/test_sim.py | 3 +++ 4 files changed, 21 insertions(+), 10 deletions(-) diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py index b91c1dde..2e60086f 100644 --- a/src/soc/simple/test/test_issuer.py +++ b/src/soc/simple/test/test_issuer.py @@ -25,15 +25,15 @@ from soc.fu.compunits.test.test_compunit import (setup_test_memory, check_sim_memory) # test with ALU data and Logical data -from soc.fu.alu.test.test_pipe_caller import ALUTestCase +#from soc.fu.alu.test.test_pipe_caller import ALUTestCase #from soc.fu.logical.test.test_pipe_caller import LogicalTestCase #from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase #from soc.fu.cr.test.test_pipe_caller import CRTestCase #from soc.fu.branch.test.test_pipe_caller import BranchTestCase -from soc.fu.spr.test.test_pipe_caller import SPRTestCase +#from soc.fu.spr.test.test_pipe_caller import SPRTestCase #from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase #from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase) -#from soc.simulator.test_helloworld_sim import HelloTestCases +from soc.simulator.test_helloworld_sim import HelloTestCases def setup_i_memory(imem, startaddr, instructions): @@ -179,16 +179,16 @@ class TestRunner(FHDLTestCase): if __name__ == "__main__": unittest.main(exit=False) suite = unittest.TestSuite() - #suite.addTest(TestRunner(HelloTestCases.test_data)) + suite.addTest(TestRunner(HelloTestCases.test_data)) #suite.addTest(TestRunner(AttnTestCase.test_data)) #suite.addTest(TestRunner(GeneralTestCases.test_data)) #suite.addTest(TestRunner(LDSTTestCase.test_data)) #suite.addTest(TestRunner(CRTestCase.test_data)) #suite.addTest(TestRunner(ShiftRotTestCase.test_data)) #suite.addTest(TestRunner(LogicalTestCase.test_data)) - suite.addTest(TestRunner(ALUTestCase.test_data)) + #suite.addTest(TestRunner(ALUTestCase.test_data)) #suite.addTest(TestRunner(BranchTestCase.test_data)) - suite.addTest(TestRunner(SPRTestCase.test_data)) + #suite.addTest(TestRunner(SPRTestCase.test_data)) runner = unittest.TextTestRunner() runner.run(suite) diff --git a/src/soc/simulator/program.py b/src/soc/simulator/program.py index 2f3d88b3..19e30b3e 100644 --- a/src/soc/simulator/program.py +++ b/src/soc/simulator/program.py @@ -13,7 +13,7 @@ import sys filedir = os.path.dirname(os.path.realpath(__file__)) memmap = os.path.join(filedir, "memmap") -bigendian = False +bigendian = True if bigendian: endian_fmt = "elf64-big" obj_fmt = "-be" diff --git a/src/soc/simulator/qemu.py b/src/soc/simulator/qemu.py index d1045f15..8b374873 100644 --- a/src/soc/simulator/qemu.py +++ b/src/soc/simulator/qemu.py @@ -1,15 +1,23 @@ from pygdbmi.gdbcontroller import GdbController import subprocess -launch_args = ['qemu-system-ppc64', +launch_args_be = ['qemu-system-ppc64', + '-machine', 'powernv9', + '-nographic', + '-s', '-S'] + +launch_args_le = ['qemu-system-ppc64le', '-machine', 'powernv9', '-nographic', '-s', '-S'] class QemuController: - def __init__(self, kernel): - args = launch_args + ['-kernel', kernel] + def __init__(self, kernel, bigendian=True): + if bigendian: + args = launch_args_be + ['-kernel', kernel] + else: + args = launch_args_le + ['-kernel', kernel] self.qemu_popen = subprocess.Popen(args, stdout=subprocess.PIPE, stdin=subprocess.PIPE) diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py index 387803c3..5d348032 100644 --- a/src/soc/simulator/test_sim.py +++ b/src/soc/simulator/test_sim.py @@ -259,6 +259,9 @@ class DecoderBase: sim = Simulator(m) def process(): + yield pdecode2.dec.bigendian.eq(1) + yield Settle() + while True: try: yield from simulator.setup_one() -- 2.30.2