From 7287ac7d28e8dd051bd5682dfbaff706d7f9c918 Mon Sep 17 00:00:00 2001 From: Lauri Kasanen Date: Mon, 16 Mar 2020 11:27:00 +0200 Subject: [PATCH] Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility --- c0/e6b0dd96796eceed81dd7308762a0289a24c0a | 101 ++++++++++++++++++++++ 1 file changed, 101 insertions(+) create mode 100644 c0/e6b0dd96796eceed81dd7308762a0289a24c0a diff --git a/c0/e6b0dd96796eceed81dd7308762a0289a24c0a b/c0/e6b0dd96796eceed81dd7308762a0289a24c0a new file mode 100644 index 0000000..ab19795 --- /dev/null +++ b/c0/e6b0dd96796eceed81dd7308762a0289a24c0a @@ -0,0 +1,101 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Mon, 16 Mar 2020 09:26:18 +0000 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jDm0n-0007gb-Hx; Mon, 16 Mar 2020 09:26:17 +0000 +Received: from mout.gmx.net ([212.227.17.20]) + by libre-riscv.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) + (Exim 4.89) (envelope-from ) id 1jDm0l-0007gV-6I + for libre-riscv-dev@lists.libre-riscv.org; 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