From 7292da748c7e074f75655457e7a6e85189578331 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 14 Oct 2018 14:33:40 +0100 Subject: [PATCH] add category descriptions --- simple_v_extension/opcodes.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/simple_v_extension/opcodes.mdwn b/simple_v_extension/opcodes.mdwn index 157be7828..478eeb778 100644 --- a/simple_v_extension/opcodes.mdwn +++ b/simple_v_extension/opcodes.mdwn @@ -4,7 +4,7 @@ Based on information from Michael Clark's riscv-meta opcodes table, this page categorises and identifies the type of parallelism that SimpleV indirectly adds on each RISC-V **standard** opcode. -* **-** - no action +* **-** no action * **sv** - a standard contiguous (optionally predicated, optionally indirected) multi-register operation where the predication for the operation is taken from the **destination** register -- 2.30.2