From 729e750fba284e8d99988a71983a6a5dd7bbb96a Mon Sep 17 00:00:00 2001 From: Wolfgang Gellerich Date: Wed, 28 Jan 2009 16:36:42 +0000 Subject: [PATCH] s390.md (*tmsi_reg): Fixed z10prop attribute. 2009-01-28 Wolfgang Gellerich * config/s390/s390.md (*tmsi_reg): Fixed z10prop attribute. (*tm_full): Fixed z10prop attribute. (*tst_extimm): Fixed z10prop attribute. (*tst_cconly_extimm): Fixed z10prop attribute. (*tstqiCCT_cconly): Fixed z10prop attribute. (*cmpsi_ccu_zerohi_rlsi): Fixed z10prop attribute. (*movsi_larl): Fixed z10prop attribute. (*movsi_zarch): Fixed z10prop attribute. (*movsi_eas): Fixed z10prop attribute. (*movhi): Fixed z10prop attribute. (*movqi): Fixed z10prop attribute. (*movstrictqi): Fixed z10prop attribute. (*mov): Fixed z10prop attribute. (*movcc): Fixed z10prop attribute. (*sethighpartdi_64): Fixed z10prop attribute. (*zero_extendhi2_z10): Fixed z10prop attribute. (*negdi2_sign_cc): Fixed z10prop attribute. (*negdi2_sign): Fixed z10prop attribute. (*absdi2_sign_cc): Fixed z10prop attribute. (*absdi2_sign): Fixed z10prop attribute. (*negabsdi2_sign_cc): Fixed z10prop attribute. (*negabsdi2_sign): Fixed z10prop attribute. (*cmp_and_trap_signed_int): Fixed z10prop attribute. (*cmp_and_trap_unsigned_int): Fixed z10prop attribute. (doloop_si64): Fixed z10prop attribute. (doloop_si31): Fixed z10prop attribute. (doloop_long): Fixed z10prop attribute. (indirect_jump): Fixed z10prop attribute. (nop): Fixed z10prop attribute. (main_base_64): Fixed z10prop attribute. (reload_base_64): Fixed z10prop attribute. From-SVN: r143734 --- gcc/ChangeLog | 34 ++++++++++++++++++ gcc/config/s390/s390.md | 77 +++++++++++++++++++++++------------------ 2 files changed, 78 insertions(+), 33 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b2e37856831..83443083cc9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,37 @@ +2009-01-28 Wolfgang Gellerich + + * config/s390/s390.md (*tmsi_reg): Fixed z10prop attribute. + (*tm_full): Fixed z10prop attribute. + (*tst_extimm): Fixed z10prop attribute. + (*tst_cconly_extimm): Fixed z10prop attribute. + (*tstqiCCT_cconly): Fixed z10prop attribute. + (*cmpsi_ccu_zerohi_rlsi): Fixed z10prop attribute. + (*movsi_larl): Fixed z10prop attribute. + (*movsi_zarch): Fixed z10prop attribute. + (*movsi_eas): Fixed z10prop attribute. + (*movhi): Fixed z10prop attribute. + (*movqi): Fixed z10prop attribute. + (*movstrictqi): Fixed z10prop attribute. + (*mov): Fixed z10prop attribute. + (*movcc): Fixed z10prop attribute. + (*sethighpartdi_64): Fixed z10prop attribute. + (*zero_extendhi2_z10): Fixed z10prop attribute. + (*negdi2_sign_cc): Fixed z10prop attribute. + (*negdi2_sign): Fixed z10prop attribute. + (*absdi2_sign_cc): Fixed z10prop attribute. + (*absdi2_sign): Fixed z10prop attribute. + (*negabsdi2_sign_cc): Fixed z10prop attribute. + (*negabsdi2_sign): Fixed z10prop attribute. + (*cmp_and_trap_signed_int): Fixed z10prop attribute. + (*cmp_and_trap_unsigned_int): Fixed z10prop attribute. + (doloop_si64): Fixed z10prop attribute. + (doloop_si31): Fixed z10prop attribute. + (doloop_long): Fixed z10prop attribute. + (indirect_jump): Fixed z10prop attribute. + (nop): Fixed z10prop attribute. + (main_base_64): Fixed z10prop attribute. + (reload_base_64): Fixed z10prop attribute. + 2009-01-28 Jakub Jelinek PR rtl-optimization/38740 diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index e8b50830d58..adcce8ab3ef 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -558,7 +558,8 @@ "@ tmh\t%0,%i1 tml\t%0,%i1" - [(set_attr "op_type" "RI")]) + [(set_attr "op_type" "RI") + (set_attr "z10prop" "z10_super,z10_super")]) (define_insn "*tm_full" [(set (reg CC_REGNUM) @@ -566,7 +567,8 @@ (match_operand:HQI 1 "immediate_operand" "n")))] "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" "tml\t%0," - [(set_attr "op_type" "RI")]) + [(set_attr "op_type" "RI") + (set_attr "z10prop" "z10_super")]) ; @@ -604,7 +606,7 @@ ltr\t%2,%0 lt\t%2,%0" [(set_attr "op_type" "RR,RXY") - (set_attr "z10prop" "z10_fr_E1,z10_fr_A3") ]) + (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) ; ltr, lt, ltgr, ltg (define_insn "*tst_cconly_extimm" @@ -617,7 +619,7 @@ ltr\t%0,%0 lt\t%2,%0" [(set_attr "op_type" "RR,RXY") - (set_attr "z10prop" "z10_fr_E1,z10_fr_A3")]) + (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) (define_insn "*tstdi" [(set (reg CC_REGNUM) @@ -715,7 +717,7 @@ cliy\t%S0,0 tml\t%0,255" [(set_attr "op_type" "SI,SIY,RI") - (set_attr "z10prop" "z10_super,z10_super,*")]) + (set_attr "z10prop" "z10_super,z10_super,z10_super")]) (define_insn "*tst" [(set (reg CC_REGNUM) @@ -856,7 +858,8 @@ "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" "clhrl\t%0,%1" [(set_attr "op_type" "RIL") - (set_attr "type" "larl")]) + (set_attr "type" "larl") + (set_attr "z10prop" "z10_super")]) ; clhrl, clghrl (define_insn "*cmp_ccu_zerohi_rldi" @@ -1527,7 +1530,7 @@ "larl\t%0,%1" [(set_attr "op_type" "RIL") (set_attr "type" "larl") - (set_attr "z10prop" "z10_super_A1")]) + (set_attr "z10prop" "z10_fwd_A1")]) (define_insn "*movsi_zarch" [(set (match_operand:SI 0 "nonimmediate_operand" @@ -1593,7 +1596,7 @@ z10_fr_E1, z10_fwd_A3, z10_fwd_A3, - z10_super, + z10_rec, z10_rec, *, *, @@ -1628,7 +1631,7 @@ (set_attr "z10prop" "z10_fwd_A1, z10_fr_E1, z10_fwd_A3, - z10_super, + z10_rec, *, *, *, @@ -1766,7 +1769,7 @@ z10_super_E1, z10_super_E1, z10_super_E1, - z10_super, + z10_rec, z10_rec, z10_rec, z10_super")]) @@ -1822,7 +1825,7 @@ z10_fwd_A1, z10_super_E1, z10_super_E1, - z10_super, + z10_rec, z10_rec, z10_super, z10_super")]) @@ -1849,7 +1852,7 @@ ic\t%0,%1 icy\t%0,%1" [(set_attr "op_type" "RX,RXY") - (set_attr "z10prop" "z10_super_E1,z10_super")]) + (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) ; ; movstricthi instruction pattern(s). @@ -2167,7 +2170,7 @@ z10_fr_E1, z10_fwd_A3, z10_fwd_A3, - z10_super, + z10_rec, z10_rec")]) ; @@ -2188,7 +2191,7 @@ ly\t%1,%0" [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") (set_attr "type" "lr,*,*,store,store,load,load") - (set_attr "z10prop" "z10_fr_E1,*,*,z10_super,z10_rec,z10_fwd_A3,z10_fwd_A3")]) + (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")]) ; ; Block move (MVC) patterns. @@ -3153,7 +3156,8 @@ (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "icmh\t%0,%2,%S1" - [(set_attr "op_type" "RSY")]) + [(set_attr "op_type" "RSY") + (set_attr "z10prop" "z10_super")]) (define_insn "*sethighpartdi_31" [(set (match_operand:DI 0 "register_operand" "=d,d") @@ -3696,7 +3700,7 @@ [(set_attr "op_type" "RXY,RRE,RIL") (set_attr "type" "*,*,larl") (set_attr "cpu_facility" "*,*,z10") - (set_attr "z10prop" "z10_fwd_A3")]) + (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")]) ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc (define_insn "*zero_extend2_extimm" @@ -6630,7 +6634,8 @@ (neg:DI (sign_extend:DI (match_dup 1))))] "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" "lcgfr\t%0,%1" - [(set_attr "op_type" "RRE")]) + [(set_attr "op_type" "RRE") + (set_attr "z10prop" "z10_c")]) (define_insn "*negdi2_sign" [(set (match_operand:DI 0 "register_operand" "=d") @@ -6638,7 +6643,8 @@ (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "lcgfr\t%0,%1" - [(set_attr "op_type" "RRE")]) + [(set_attr "op_type" "RRE") + (set_attr "z10prop" "z10_c")]) ; lcr, lcgr (define_insn "*neg2_cc" @@ -6774,7 +6780,8 @@ (abs:DI (sign_extend:DI (match_dup 1))))] "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" "lpgfr\t%0,%1" - [(set_attr "op_type" "RRE")]) + [(set_attr "op_type" "RRE") + (set_attr "z10prop" "z10_c")]) (define_insn "*absdi2_sign" [(set (match_operand:DI 0 "register_operand" "=d") @@ -6782,7 +6789,8 @@ (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "lpgfr\t%0,%1" - [(set_attr "op_type" "RRE")]) + [(set_attr "op_type" "RRE") + (set_attr "z10prop" "z10_c")]) ; lpr, lpgr (define_insn "*abs2_cc" @@ -6890,7 +6898,8 @@ (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" "lngfr\t%0,%1" - [(set_attr "op_type" "RRE")]) + [(set_attr "op_type" "RRE") + (set_attr "z10prop" "z10_c")]) (define_insn "*negabsdi2_sign" [(set (match_operand:DI 0 "register_operand" "=d") @@ -6899,7 +6908,8 @@ (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "lngfr\t%0,%1" - [(set_attr "op_type" "RRE")]) + [(set_attr "op_type" "RRE") + (set_attr "z10prop" "z10_c")]) ; lnr, lngr (define_insn "*negabs2_cc" @@ -7516,7 +7526,7 @@ cit%C0\t%1,%h2" [(set_attr "op_type" "RRF,RIE") (set_attr "type" "branch") - (set_attr "z10prop" "z10_c,*")]) + (set_attr "z10prop" "z10_super_c,z10_super")]) ; clrt, clgrt, clfit, clgit (define_insn "*cmp_and_trap_unsigned_int" @@ -7530,7 +7540,7 @@ clit%C0\t%1,%x2" [(set_attr "op_type" "RRF,RIE") (set_attr "type" "branch") - (set_attr "z10prop" "z10_c,*")]) + (set_attr "z10prop" "z10_super_c,z10_super")]) ;; ;;- Loop instructions. @@ -7594,7 +7604,7 @@ [(set_attr "op_type" "RI") ; Strictly speaking, the z10 properties are valid for brct only, however, it does not ; hurt us in the (rare) case of ahi. - (set_attr "z10prop" "z10_super") + (set_attr "z10prop" "z10_super_E1") (set_attr "type" "branch") (set (attr "length") (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) @@ -7636,7 +7646,7 @@ [(set_attr "op_type" "RI") ; Strictly speaking, the z10 properties are valid for brct only, however, it does not ; hurt us in the (rare) case of ahi. - (set_attr "z10prop" "z10_super") + (set_attr "z10prop" "z10_super_E1") (set_attr "type" "branch") (set (attr "length") (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) @@ -7667,7 +7677,8 @@ (if_then_else (match_operand 0 "register_operand" "") (const_string "RR") (const_string "RX"))) (set_attr "type" "branch") - (set_attr "atype" "agen")]) + (set_attr "atype" "agen") + (set_attr "z10prop" "z10_cobra")]) (define_insn_and_split "doloop_di" [(set (pc) @@ -7705,7 +7716,7 @@ [(set_attr "op_type" "RI") ; Strictly speaking, the z10 properties are valid for brct only, however, it does not ; hurt us in the (rare) case of ahi. - (set_attr "z10prop" "z10_super") + (set_attr "z10prop" "z10_super_E1") (set_attr "type" "branch") (set (attr "length") (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) @@ -7772,8 +7783,7 @@ (if_then_else (match_operand 0 "register_operand" "") (const_string "RR") (const_string "RX"))) (set_attr "type" "branch") - (set_attr "atype" "agen") - (set_attr "z10prop" "z10_super")]) + (set_attr "atype" "agen")]) ; ; casesi instruction pattern(s). @@ -8468,7 +8478,8 @@ [(const_int 0)] "" "lr\t0,0" - [(set_attr "op_type" "RR")]) + [(set_attr "op_type" "RR") + (set_attr "z10prop" "z10_fr_E1")]) (define_insn "nop1" [(const_int 1)] @@ -8536,7 +8547,7 @@ "larl\t%0,%1" [(set_attr "op_type" "RIL") (set_attr "type" "larl") - (set_attr "z10prop" "z10_super_A1")]) + (set_attr "z10prop" "z10_fwd_A1")]) (define_insn "main_pool" [(set (match_operand 0 "register_operand" "=a") @@ -8564,7 +8575,7 @@ "larl\t%0,%1" [(set_attr "op_type" "RIL") (set_attr "type" "larl") - (set_attr "z10prop" "z10_super_A1")]) + (set_attr "z10prop" "z10_fwd_A1")]) (define_insn "pool" [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] -- 2.30.2