From 72a239266b84033e539283d50ca0b3c50e630463 Mon Sep 17 00:00:00 2001 From: Anuj Phogat Date: Fri, 10 Nov 2017 14:22:18 -0800 Subject: [PATCH] intel/genxml: Add Cache Mode SubSlice Register to gen10.xml Signed-off-by: Anuj Phogat Reviewed-by: Rafael Antognolli --- src/intel/genxml/gen10.xml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml index a7ae49ae659..a6b8f48fda5 100644 --- a/src/intel/genxml/gen10.xml +++ b/src/intel/genxml/gen10.xml @@ -3752,4 +3752,16 @@ + + + + + + + + + + + + -- 2.30.2