From 72c52641d3b5c9d899586445a1f22686d4871b72 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 14 Oct 2018 05:06:46 +0100 Subject: [PATCH] bit of a mess: attempted to create a complete arithmetic overload had to back most of it out, and left in a change to the amo* functions passing in a 2nd parameter to the higher-order-function --- riscv/insn_template_sv.cc | 2 +- riscv/insns/amoadd_d.h | 3 +- riscv/insns/amoadd_w.h | 3 +- riscv/insns/amoand_d.h | 3 +- riscv/insns/amoand_w.h | 3 +- riscv/insns/amomax_d.h | 3 +- riscv/insns/amomax_w.h | 3 +- riscv/insns/amomaxu_d.h | 3 +- riscv/insns/amomaxu_w.h | 4 +- riscv/insns/amomin_d.h | 4 +- riscv/insns/amomin_w.h | 4 +- riscv/insns/amominu_d.h | 3 +- riscv/insns/amominu_w.h | 4 +- riscv/insns/amoor_d.h | 3 +- riscv/insns/amoor_w.h | 3 +- riscv/insns/amoswap_d.h | 3 +- riscv/insns/amoswap_w.h | 3 +- riscv/insns/amoxor_d.h | 3 +- riscv/insns/amoxor_w.h | 3 +- riscv/mmu.h | 4 +- riscv/processor.h | 2 +- riscv/sv_decode.h | 5 ++ riscv/sv_insn_redirect.cc | 133 ++++++++++++++++++++++++++++---------- riscv/sv_insn_redirect.h | 42 ++++++------ riscv/sv_reg.h | 37 ++++++----- 25 files changed, 191 insertions(+), 92 deletions(-) diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc index 46d0887..c80477a 100644 --- a/riscv/insn_template_sv.cc +++ b/riscv/insn_template_sv.cc @@ -87,7 +87,7 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc) reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc) { int xlen = ISASZ; - reg_t npc = sext_xlen(pc + insn_length(INSNCODE)); + reg_t npc = _sext_xlen(pc + insn_length(INSNCODE)); // messy way to do it: insn_t is used elsewhere in a union, // so cannot create virtual functions. // a workaround is to grab the bits from the insn_t diff --git a/riscv/insns/amoadd_d.h b/riscv/insns/amoadd_d.h index 6090fbc..009cb21 100644 --- a/riscv/insns/amoadd_d.h +++ b/riscv/insns/amoadd_d.h @@ -1,3 +1,4 @@ require_extension('A'); require_rv64; -WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return lhs + RS2; })); +WRITE_RD(MMU.amo_uint64(RS1, RS2, + [&](uint64_t lhs, uint64_t rhs) { return lhs + rhs; })); diff --git a/riscv/insns/amoadd_w.h b/riscv/insns/amoadd_w.h index 2c6471a..98bd3ed 100644 --- a/riscv/insns/amoadd_w.h +++ b/riscv/insns/amoadd_w.h @@ -1,2 +1,3 @@ require_extension('A'); -WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return lhs + RS2; }))); +WRITE_RD(sext32(MMU.amo_uint32(RS1, RS2, + [&](uint32_t lhs, uint32_t rhs) { return lhs + rhs; }))); diff --git a/riscv/insns/amoand_d.h b/riscv/insns/amoand_d.h index 80aea18..3877e30 100644 --- a/riscv/insns/amoand_d.h +++ b/riscv/insns/amoand_d.h @@ -1,3 +1,4 @@ require_extension('A'); require_rv64; -WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return lhs & RS2; })); +WRITE_RD(MMU.amo_uint64(RS1, RS2, + [&](uint64_t lhs, uint64_t rhs) { return lhs & rhs; })); diff --git a/riscv/insns/amoand_w.h b/riscv/insns/amoand_w.h index f7e1ba7..fa9e665 100644 --- a/riscv/insns/amoand_w.h +++ b/riscv/insns/amoand_w.h @@ -1,2 +1,3 @@ require_extension('A'); -WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return lhs & RS2; }))); +WRITE_RD(sext32(MMU.amo_uint32(RS1, RS2, + [&](uint32_t lhs, uint32_t rhs) { return lhs & rhs; }))); diff --git a/riscv/insns/amomax_d.h b/riscv/insns/amomax_d.h index 496d8ad..bd798b4 100644 --- a/riscv/insns/amomax_d.h +++ b/riscv/insns/amomax_d.h @@ -1,3 +1,4 @@ require_extension('A'); require_rv64; -WRITE_RD(MMU.amo_uint64(RS1, [&](int64_t lhs) { return std::max(lhs, int64_t(RS2)); })); +WRITE_RD(MMU.amo_uint64(RS1, RS2, + [&](int64_t lhs, uint64_t rhs) { return std::max(lhs, int64_t(rhs)); })); diff --git a/riscv/insns/amomax_w.h b/riscv/insns/amomax_w.h index 757bdd2..80cc527 100644 --- a/riscv/insns/amomax_w.h +++ b/riscv/insns/amomax_w.h @@ -1,2 +1,3 @@ require_extension('A'); -WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](int32_t lhs) { return std::max(lhs, int32_t(RS2)); }))); +WRITE_RD(sext32(MMU.amo_uint32(RS1, RS2, + [&](int32_t lhs, int32_t rhs) { return std::max(lhs, int32_t(rhs)); }))); diff --git a/riscv/insns/amomaxu_d.h b/riscv/insns/amomaxu_d.h index 12b1733..7f6f252 100644 --- a/riscv/insns/amomaxu_d.h +++ b/riscv/insns/amomaxu_d.h @@ -1,3 +1,4 @@ require_extension('A'); require_rv64; -WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return std::max(lhs, RS2); })); +WRITE_RD(MMU.amo_uint64(RS1, RS2, + [&](uint64_t lhs, uint64_t rhs) { return (lhs > rhs) ? lhs : rhs; })); diff --git a/riscv/insns/amomaxu_w.h b/riscv/insns/amomaxu_w.h index 538df1c..62c5110 100644 --- a/riscv/insns/amomaxu_w.h +++ b/riscv/insns/amomaxu_w.h @@ -1,2 +1,4 @@ require_extension('A'); -WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return std::max(lhs, uint32_t(RS2)); }))); +WRITE_RD(sext32(MMU.amo_uint32(RS1, RS2, + [&](uint32_t lhs, uint32_t rhs) + { return std::max(lhs, uint32_t(rhs)); }))); diff --git a/riscv/insns/amomin_d.h b/riscv/insns/amomin_d.h index 725d983..2837cdf 100644 --- a/riscv/insns/amomin_d.h +++ b/riscv/insns/amomin_d.h @@ -1,3 +1,5 @@ require_extension('A'); require_rv64; -WRITE_RD(MMU.amo_uint64(RS1, [&](int64_t lhs) { return std::min(lhs, int64_t(RS2)); })); +WRITE_RD(MMU.amo_uint64(RS1, RS2, + [&](int64_t lhs, uint64_t rhs) + { return std::min(lhs, int64_t(rhs)); })); diff --git a/riscv/insns/amomin_w.h b/riscv/insns/amomin_w.h index ee53faa..87176d1 100644 --- a/riscv/insns/amomin_w.h +++ b/riscv/insns/amomin_w.h @@ -1,2 +1,4 @@ require_extension('A'); -WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](int32_t lhs) { return std::min(lhs, int32_t(RS2)); }))); +WRITE_RD(sext32(MMU.amo_uint32(RS1, RS2, + [&](int32_t lhs, int32_t rhs) + { return std::min(lhs, int32_t(rhs)); }))); diff --git a/riscv/insns/amominu_d.h b/riscv/insns/amominu_d.h index 15b6c0a..1bef71c 100644 --- a/riscv/insns/amominu_d.h +++ b/riscv/insns/amominu_d.h @@ -1,3 +1,4 @@ require_extension('A'); require_rv64; -WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return std::min(lhs, RS2); })); +WRITE_RD(MMU.amo_uint64(RS1, RS2, + [&](uint64_t lhs, uint64_t rhs) { return (lhs < rhs) ? lhs : rhs; })); diff --git a/riscv/insns/amominu_w.h b/riscv/insns/amominu_w.h index 52e1141..c4a5553 100644 --- a/riscv/insns/amominu_w.h +++ b/riscv/insns/amominu_w.h @@ -1,2 +1,4 @@ require_extension('A'); -WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return std::min(lhs, uint32_t(RS2)); }))); +WRITE_RD(sext32(MMU.amo_uint32(RS1, RS2, + [&](uint32_t lhs, uint32_t rhs) + { return std::min(lhs, uint32_t(rhs)); }))); diff --git a/riscv/insns/amoor_d.h b/riscv/insns/amoor_d.h index de87627..dfcae38 100644 --- a/riscv/insns/amoor_d.h +++ b/riscv/insns/amoor_d.h @@ -1,3 +1,4 @@ require_extension('A'); require_rv64; -WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return lhs | RS2; })); +WRITE_RD(MMU.amo_uint64(RS1, RS2, + [&](uint64_t lhs, uint64_t rhs) { return lhs | rhs; })); diff --git a/riscv/insns/amoor_w.h b/riscv/insns/amoor_w.h index 3455981..ae14a2f 100644 --- a/riscv/insns/amoor_w.h +++ b/riscv/insns/amoor_w.h @@ -1,2 +1,3 @@ require_extension('A'); -WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return lhs | RS2; }))); +WRITE_RD(sext32(MMU.amo_uint32(RS1, RS2, + [&](uint32_t lhs, uint32_t rhs) { return lhs | rhs; }))); diff --git a/riscv/insns/amoswap_d.h b/riscv/insns/amoswap_d.h index e1bffde..b79f0e3 100644 --- a/riscv/insns/amoswap_d.h +++ b/riscv/insns/amoswap_d.h @@ -1,3 +1,4 @@ require_extension('A'); require_rv64; -WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return RS2; })); +WRITE_RD(MMU.amo_uint64(RS1, RS2, + [&](uint64_t lhs, uint64_t rhs) { return rhs; })); diff --git a/riscv/insns/amoswap_w.h b/riscv/insns/amoswap_w.h index 0f78369..94fc2be 100644 --- a/riscv/insns/amoswap_w.h +++ b/riscv/insns/amoswap_w.h @@ -1,2 +1,3 @@ require_extension('A'); -WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return RS2; }))); +WRITE_RD(sext32(MMU.amo_uint32(RS1, RS2, + [&](uint32_t lhs, uint32_t rhs) { return rhs; }))); diff --git a/riscv/insns/amoxor_d.h b/riscv/insns/amoxor_d.h index 1b3c0bf..412ecbd 100644 --- a/riscv/insns/amoxor_d.h +++ b/riscv/insns/amoxor_d.h @@ -1,3 +1,4 @@ require_extension('A'); require_rv64; -WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return lhs ^ RS2; })); +WRITE_RD(MMU.amo_uint64(RS1, RS2, + [&](uint64_t lhs, uint64_t rhs) { return lhs ^ rhs; })); diff --git a/riscv/insns/amoxor_w.h b/riscv/insns/amoxor_w.h index a1ea82f..8274fde 100644 --- a/riscv/insns/amoxor_w.h +++ b/riscv/insns/amoxor_w.h @@ -1,2 +1,3 @@ require_extension('A'); -WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return lhs ^ RS2; }))); +WRITE_RD(sext32(MMU.amo_uint32(RS1, RS2, + [&](uint32_t lhs, uint32_t rhs) { return lhs ^ rhs; }))); diff --git a/riscv/mmu.h b/riscv/mmu.h index f66eb00..3f111a3 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -135,12 +135,12 @@ public: // template for functions that perform an atomic memory operation #define amo_func(type) \ template \ - type##_t amo_##type(reg_t addr, op f) { \ + type##_t amo_##type(reg_t addr, reg_t rhs, op f) { \ if (addr & (sizeof(type##_t)-1)) \ throw trap_store_address_misaligned(addr); \ try { \ auto lhs = load_##type(addr); \ - store_##type(addr, f(lhs)); \ + store_##type(addr, f(lhs, rhs)); \ return lhs; \ } catch (trap_load_page_fault& t) { \ /* AMO faults should be reported as store faults */ \ diff --git a/riscv/processor.h b/riscv/processor.h index 80d33b6..1ffdfab 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -11,8 +11,8 @@ #include #include "debug_rom_defines.h" #ifdef SPIKE_SIMPLEV -#include "sv_decode.h" #include "sv_insn_redirect.h" +#include "sv_decode.h" #endif class processor_t; diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h index adbb0d6..b2b73a4 100644 --- a/riscv/sv_decode.h +++ b/riscv/sv_decode.h @@ -5,6 +5,7 @@ #include "sv.h" #include "decode.h" +//#include "sv_reg.h" //#include "processor.h" #define REG_RD 0x1 @@ -33,6 +34,10 @@ public: prd(p_rd), prs1(p_rs1), prs2(p_rs2), prs3(p_rs3), save_branch_addr(0) {} + uint64_t rvc_imm() { return (insn_t::rvc_imm()); } + uint64_t u_imm() { return (insn_t::u_imm()); } + uint64_t i_imm() { return (insn_t::i_imm()); } + uint64_t s_imm() { return (insn_t::s_imm()); } uint64_t _rvc_spoffs_imm(uint64_t elwidth, uint64_t baseoffs); uint64_t rvc_lwsp_imm() { return _rvc_spoffs_imm(4, insn_t::rvc_lwsp_imm()); } uint64_t rvc_ldsp_imm() { return _rvc_spoffs_imm(8, insn_t::rvc_ldsp_imm()); } diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc index 07eb84f..02edba5 100644 --- a/riscv/sv_insn_redirect.cc +++ b/riscv/sv_insn_redirect.cc @@ -19,16 +19,23 @@ void (sv_proc_t::WRITE_FRD)(freg_t value) DO_WRITE_FREG( _insn->rd(), freg(value) ); } +/* void (sv_proc_t::WRITE_RD)(bool value) { WRITE_REG( _insn->rd(), value ? 1 : 0); } - void (sv_proc_t::WRITE_RD)(sv_reg_t value) { WRITE_REG( _insn->rd(), value.get_data() ); } +*/ + +void (sv_proc_t::WRITE_RD)(uint64_t value) +{ + WRITE_REG( _insn->rd(), value ); // XXX TODO: replace properly +} +/* void (sv_proc_t::WRITE_RD)(int_fast64_t value) { WRITE_REG( _insn->rd(), value ); // XXX TODO: replace properly @@ -38,6 +45,7 @@ void (sv_proc_t::WRITE_RD)(uint_fast64_t value) { WRITE_REG( _insn->rd(), value ); // XXX TODO: replace properly } +*/ /* reg_t (sv_proc_t::READ_REG)(uint64_t i) @@ -46,82 +54,94 @@ reg_t (sv_proc_t::READ_REG)(uint64_t i) } */ -sv_reg_t sv_proc_t::get_rs1() +reg_t sv_proc_t::get_rs1() { - return sv_uint64_t(_insn->p->get_state()->XPR[_insn->rs1()]); + return (_insn->p->get_state()->XPR[_insn->rs1()]); } -sv_reg_t sv_proc_t::get_rs2() +reg_t sv_proc_t::get_rs2() { - return sv_uint64_t(_insn->p->get_state()->XPR[_insn->rs2()]); + return (_insn->p->get_state()->XPR[_insn->rs2()]); } -sv_reg_t sv_proc_t::get_rvc_rs1s() +reg_t sv_proc_t::get_rvc_rs1s() { - return sv_uint64_t(_insn->p->get_state()->XPR[_insn->rvc_rs1s()]); + return (_insn->p->get_state()->XPR[_insn->rvc_rs1s()]); } -sv_reg_t sv_proc_t::get_rvc_rs2s() +reg_t sv_proc_t::get_rvc_rs2s() { - return sv_uint64_t(_insn->p->get_state()->XPR[_insn->rvc_rs2s()]); + return (_insn->p->get_state()->XPR[_insn->rvc_rs2s()]); } -sv_reg_t sv_proc_t::get_rvc_rs1() +reg_t sv_proc_t::get_rvc_rs1() { - return sv_uint64_t(_insn->p->get_state()->XPR[_insn->rvc_rs1()]); + return (_insn->p->get_state()->XPR[_insn->rvc_rs1()]); } -sv_reg_t sv_proc_t::get_rvc_rs2() +reg_t sv_proc_t::get_rvc_rs2() { - return sv_uint64_t(_insn->p->get_state()->XPR[_insn->rvc_rs2()]); + return (_insn->p->get_state()->XPR[_insn->rvc_rs2()]); } -sv_reg_t sv_proc_t::get_rs3() +reg_t sv_proc_t::get_rs3() { - return sv_uint64_t(_insn->p->get_state()->XPR[_insn->rs3()]); + return (_insn->p->get_state()->XPR[_insn->rs3()]); } -sv_reg_t sv_proc_t::get_rvc_sp() +reg_t sv_proc_t::get_rvc_sp() { - return sv_uint64_t(_insn->p->get_state()->XPR[X_SP]); + return (_insn->p->get_state()->XPR[X_SP]); } -sv_reg_t sv_proc_t::uint64_max() +reg_t sv_proc_t::uint64_max() { - return sv_uint64_t((UINT64_C(18446744073709551615))); + return ((UINT64_C(18446744073709551615))); } -sv_reg_t (sv_proc_t::sext_xlen)(sv_reg_t v) +/* +reg_t (sv_proc_t::sext_xlen)(uint64_t x) { - uint64_t x = v.as_uint64(); x = (((sreg_t)(x) << (64-xlen)) >> (64-xlen)); return sv_uint64_t(x); } +*/ +reg_t (sv_proc_t::sext_xlen)(reg_t x) +{ + //uint64_t x = v.as_uint64(); + x = (((sreg_t)(x) << (64-xlen)) >> (64-xlen)); + return x; + //return sv_uint64_t(x); +} -sv_reg_t (sv_proc_t::zext_xlen)(sv_reg_t v) +reg_t (sv_proc_t::zext_xlen)(reg_t x) { - uint64_t x = v.as_uint64(); + //uint64_t x = v.as_uint64(); x = (((reg_t)(x) << (64-xlen)) >> (64-xlen)); - return sv_uint64_t(x); + return x; + //return sv_uint64_t(x); } -sv_reg_t (sv_proc_t::sext32)(uint_fast32_t v) +/* +reg_t (sv_proc_t::sext32)(uint_fast32_t v) { return sext32((uint64_t)v); // XXX TODO do properly } - -sv_reg_t (sv_proc_t::sext32)(sv_reg_t v) +*/ +reg_t (sv_proc_t::sext32)(reg_t x) { - uint64_t x = v.as_uint64(); + //uint64_t x = v.as_uint64(); x = ((sreg_t)(int32_t)(x)); - return sv_uint64_t(x); + return x; + //return sv_uint64_t(x); } -sv_reg_t (sv_proc_t::zext32)(sv_reg_t v) +reg_t (sv_proc_t::zext32)(reg_t x) { - uint64_t x = v.as_uint64(); + //uint64_t x = v.as_uint64(); x = ((reg_t)(uint32_t)(x)); - return sv_uint64_t(x); + return x; + //return sv_uint64_t(x); } freg_t sv_proc_t::get_frs1() @@ -134,6 +154,7 @@ freg_t sv_proc_t::get_frs2() return READ_FREG(_insn->rs2()); } +/* sv_reg_t sv_reg_t::make_sv_int64_t (int64_t v) const { return sv_sreg_t(v); @@ -145,8 +166,54 @@ sv_reg_t sv_reg_t::make_sv_uint64_t (uint64_t v) const } -sv_reg_t::operator sv_sreg_t () const +sv_reg_t::operator sv_sreg_t () { return sv_sreg_t ( as_uint64() ); } +sv_reg_t::operator int32_t () +{ + uint64_t x = get_data(); + sreg_t _x = (sreg_t) x; + sv_sreg_t y = sv_sreg_t ( _x ); + return y; +} + + +sv_reg_t::operator uint16_t () +{ + uint64_t x = get_data(); + uint16_t _x = (uint16_t) x; + sv_uint16_t y = sv_uint16_t ( _x ); + return y; +} + + +sv_reg_t::operator uint8_t () // XXX TODO, make_sv_char_t +{ + uint64_t x = get_data(); + uint8_t _x = (uint8_t) x; + sv_uint64_t y = sv_uint64_t ( _x ); + return y; +} + +sv_reg_t::operator char () // XXX TODO, make_sv_char_t +{ + uint64_t x = get_data(); + char _x = (char) x; + sv_sreg_t y = sv_sreg_t ( _x ); + return y; +} + +sv_reg_t::operator uint32_t () // TODO, make_sv_uint32_t + { return make_sv_uint64_t( (sreg_t) (as_uint64()) ); } +sv_reg_t::operator sreg_t () + { return make_sv_int64_t( (sreg_t) (as_uint64()) ); } + +sv_reg_t::operator reg_t () +{ + uint64_t x = get_data(); + sv_uint64_t y = sv_uint64_t ( x ); + return y; +} +*/ diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h index 158e42f..29f680d 100644 --- a/riscv/sv_insn_redirect.h +++ b/riscv/sv_insn_redirect.h @@ -4,7 +4,7 @@ #include #include "decode.h" #include "sv_decode.h" -#include "sv_reg.h" +//#include "sv_reg.h" #undef RS1 #undef RS2 @@ -43,10 +43,11 @@ class sv_proc_t { public: sv_proc_t(processor_t *_p) : p(_p), _insn(NULL), xlen(0) {} - void (WRITE_RD)(bool value); // f32_eq calls this: XXX TODO investigate - void (WRITE_RD)(sv_reg_t value); - void (WRITE_RD)(int_fast64_t value); // XXX TODO investigate - void (WRITE_RD)(uint_fast64_t value); // XXX TODO investigate + //void (WRITE_RD)(bool value); // f32_eq calls this: XXX TODO investigate + //void (WRITE_RD)(sv_reg_t &value); + //void (WRITE_RD)(int_fast64_t value); // XXX TODO investigate + //void (WRITE_RD)(uint_fast64_t value); // XXX TODO investigate + void (WRITE_RD)(uint64_t value); // XXX TODO investigate void (WRITE_FRD)(freg_t value); void (WRITE_FRD)(float64_t value); void (WRITE_FRD)(float32_t value); @@ -70,27 +71,28 @@ public: this->insn._insn = i; } - sv_reg_t get_rs1(); - sv_reg_t get_rs2(); - sv_reg_t get_rs3(); + reg_t get_rs1(); + reg_t get_rs2(); + reg_t get_rs3(); - sv_reg_t get_rvc_sp(); - sv_reg_t get_rvc_rs1(); - sv_reg_t get_rvc_rs2(); - sv_reg_t get_rvc_rs1s(); - sv_reg_t get_rvc_rs2s(); + reg_t get_rvc_sp(); + reg_t get_rvc_rs1(); + reg_t get_rvc_rs2(); + reg_t get_rvc_rs1s(); + reg_t get_rvc_rs2s(); - sv_reg_t uint64_max(); + reg_t uint64_max(); freg_t get_frs1(); freg_t get_frs2(); - //sv_reg_t (sext_xlen)(reg_t &v); // WARNING... - sv_reg_t (zext_xlen)(sv_reg_t v); - sv_reg_t (sext_xlen)(sv_reg_t v); - sv_reg_t (sext32)(uint_fast32_t v); // XXX TODO - sv_reg_t (sext32)(sv_reg_t v); - sv_reg_t (zext32)(sv_reg_t v); + reg_t (sext_xlen)(reg_t v); // WARNING... + reg_t (zext_xlen)(reg_t v); + //reg_t (sext_xlen)(sv_reg_t &v); + //reg_t (sext32)(uint_fast32_t v); // XXX TODO + reg_t (sext32)(reg_t v); + //reg_t (sext32)(sv_reg_t &v); + reg_t (zext32)(reg_t v); #include "sv_insn_decl.h" }; diff --git a/riscv/sv_reg.h b/riscv/sv_reg.h index 7bf35be..6a69f28 100644 --- a/riscv/sv_reg.h +++ b/riscv/sv_reg.h @@ -6,11 +6,13 @@ #define DECL_1OP( op ) \ bool operator op () const { \ - return op (this->as_uint64()); } + return op (this->as_uint64()); } #define DECL_BOP( op ) \ bool operator op (const sv_reg_t& rhs) const { \ - return this->as_uint64() op rhs.as_uint64(); } + return this->as_uint64() op rhs.as_uint64(); } \ + bool operator op (reg_t rhs) const { \ + return this->as_uint64() op rhs; } #define DECL_BOPE( op ) \ bool operator op (int rhs) const { \ @@ -26,7 +28,9 @@ sv_reg_t operator op (const sreg_t& rhs) const { \ return make_##type( (this->as_uint64() op rhs) ); } \ sv_reg_t operator op (int rhs) const { \ - return make_##type( (this->as_uint64() op rhs) ); } + return make_##type( (this->as_uint64() op rhs) ); } \ + sv_reg_t operator op (uint32_t rhs) const { \ + return make_##type( (this->as_uint64() op rhs) ); } #define op_bneg ~ #define op_xor ^ @@ -53,7 +57,7 @@ class sv_reg_t { public: virtual ~sv_reg_t() {} // using a type which accommodates all values - virtual uint64_t as_uint64() const { return 0; }; + virtual uint64_t as_uint64() const = 0; public: DECL_BOP( op_ge ) @@ -76,20 +80,17 @@ public: DECL_OP( sv_uint64_t, op_sl ) DECL_OP( sv_uint64_t, op_sr ) - operator char () const // XXX TODO, make_sv_char_t - { return make_sv_int64_t( (sreg_t) (as_uint64()) ); } - operator int32_t () // XXX TODO, make_sv_char_t - { return make_sv_int64_t( (sreg_t) (as_uint64()) ); } - operator uint32_t () const // TODO, make_sv_uint32_t - { return make_sv_uint64_t( (sreg_t) (as_uint64()) ); } - operator sv_sreg_t () const; - operator sreg_t () const - { return make_sv_int64_t( (sreg_t) (as_uint64()) ); } - operator reg_t () const - { return make_sv_uint64_t( (reg_t) (as_uint64()) ); } - //operator uint_fast64_t () const + operator uint8_t (); + operator char (); + operator uint32_t (); + operator int32_t (); + operator uint16_t (); + operator sv_sreg_t () ; + operator sreg_t () ; + operator reg_t () ; + //operator uint_fast64_t () const // { return make_sv_uint64_t( (reg_t) (as_uint64()) ); } - //operator int_fast64_t () const + //operator int_fast64_t () const //{ return make_sv_int64_t( (sreg_t) (as_uint64()) ); } // ... public: @@ -120,6 +121,8 @@ private: class sv_uint16_t : public sv_reg_t { // ... +public: + sv_uint16_t(uint16_t v) : data(v) {} private: virtual uint64_t as_uint64() const { return this->data; } private: -- 2.30.2