From 72d4fcd405ceebc4322a3c890c4d312d942602a8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 2 Jun 2020 18:02:11 +0100 Subject: [PATCH] add 2nd write-reg for LD/ST Update mode --- src/soc/decoder/power_decoder2.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 09cad542..9510eb04 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -394,6 +394,7 @@ class Decode2ToExecute1Type(RecordObject): self.fn_unit = Signal(Function, reset_less=True) self.nia = Signal(64, reset_less=True) self.write_reg = Data(5, name="rego") + self.write_ea = Data(5, name="ea") # for LD/ST in update mode self.read_reg1 = Data(5, name="reg1") self.read_reg2 = Data(5, name="reg2") self.read_reg3 = Data(5, name="reg3") @@ -526,7 +527,11 @@ class PowerDecode2(Elaboratable): comb += self.e.byte_reverse.eq(self.dec.op.br) comb += self.e.sign_extend.eq(self.dec.op.sgn_ext) - comb += self.e.update.eq(self.dec.op.upd) # LD/ST "update" mode + + # LD/ST "update" mode. if set, 2nd write is RA (same as read reg A) + comb += self.e.update.eq(self.dec.op.upd) + with m.If(self.e.update): + comb += self.e.write_ea.eq(dec_a.reg_out) -- 2.30.2