From 7332e858052c3a9da296f8ad9220cfa98e23c5bc Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 22 Nov 2023 14:32:39 +0000 Subject: [PATCH] --- nlnet_2023_svp64_riscv.mdwn | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/nlnet_2023_svp64_riscv.mdwn b/nlnet_2023_svp64_riscv.mdwn index e398ee66c..6aae97155 100644 --- a/nlnet_2023_svp64_riscv.mdwn +++ b/nlnet_2023_svp64_riscv.mdwn @@ -47,18 +47,19 @@ EUR $50,000. # Explain what the requested budget will be used for? -* Research and assessment of ARM7 and i486 (both on opencores.org) - as to their feasibility for applying Simple-V Prefixing * Assessment of the missing RISC-V instructions (only 96 where Power ISA SFFS is 214) which are present in Power ISA 3.0 * Implementation of the missing RISC-V instructions that bring - it up to par with Power ISA -* Assessment of application of Simple-V Prefixing to SVP64, + it up to par with Power ISA, in the Scalar ISA space. +* Assessment of application of Simple-V Vector Prefixing to SVP64, modernising the work already done four years ago under NLnet Grant 2019-10-012 +* Implementing Simple-V * Upgrading sv-spike which was completed four years ago with an early prototype Simple-V Specification +* Research and assessment of ARM7 and i486 (both on opencores.org) + as to their feasibility for applying Simple-V Prefixing # Does the project have other funding sources, both past and present? -- 2.30.2