From 734034a8727023fdb74c9a6acd2cb6d1bfe3e81c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Sep 2019 18:13:46 -0700 Subject: [PATCH] Add an ASCII drawing --- techlibs/xilinx/abc_model.v | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 504f8a0d8..109804f09 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -48,12 +48,31 @@ endmodule // With abc_map.v responsible for disconnecting inputs to // the combinatorial DSP48E1 model by a register (e.g. // disconnecting A when AREG, MREG or PREG is enabled) -// this mux captures the existence of a replacement path -// between AREG/BREG/CREG/etc. and P/PCOUT. +// this blackbox captures the existence of a replacement +// path between AREG/BREG/CREG/etc. and P/PCOUT. // Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at -// the mux at zero time, the combinatorial delay through +// the box at zero time, the combinatorial delay through // these muxes thus represents the clock-to-q delay at // P/PCOUT. +// Doing so should means that ABC is able to analyse the +// worst-case delay through to P. +// However, the true value of being as complete as this is +// questionable since if AREG=1 and BREG=0 (as below) +// then the worse-case path would very likely be through B +// and very unlikely to be through AREG.Q...? +// +// In graphical form: +// +// NEW "PI" >>---+ +// for AREG.Q | +// | +// +---------+ | __ +// A --X X-| | +--| \ +// | DSP48E1 |P | |--- P +// | AREG=1 |-------|__/ +// B ------| | +// +---------+ +// (* abc_box_id=2100 *) module \$__ABC_DSP48E1_MULT_P_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); endmodule -- 2.30.2