From 7351fcd834a3265a400577818495539add70454f Mon Sep 17 00:00:00 2001
From: Konstantinos Margaritis <konstantinos.margaritis@vectorcamp.gr>
Date: Sun, 30 Apr 2023 18:10:35 +0000
Subject: [PATCH] do proper rounding, no rounding for SH=0 (for now), add tests

---
 openpower/isa/butterfly.mdwn              | 39 +++++++++++++++--------
 src/openpower/test/alu/maddsubrs_cases.py | 18 +++++++++--
 2 files changed, 42 insertions(+), 15 deletions(-)

diff --git a/openpower/isa/butterfly.mdwn b/openpower/isa/butterfly.mdwn
index 94840b03..1446af11 100644
--- a/openpower/isa/butterfly.mdwn
+++ b/openpower/isa/butterfly.mdwn
@@ -13,19 +13,32 @@ Pseudo-code:
     n <- SH
     sum <- (RT) + (RA)
     diff <- (RT) - (RA)
-    prod1 <- MULS(RB, sum)[XLEN:(XLEN*2)-1] + 1
-    prod2 <- MULS(RB, diff)[XLEN:(XLEN*2)-1] + 1
-    res1 <- ROTL64(prod1, XLEN-n)
-    res2 <- ROTL64(prod2, XLEN-n)
-    m <- MASK(n, (XLEN-1))
-    signbit1 <- res1[0]
-    signbit2 <- res2[0]
-    smask1 <- ([signbit1]*XLEN) & ¬m
-    smask2 <- ([signbit2]*XLEN) & ¬m
-    s64_1 <- [0]*(XLEN-1) || signbit1
-    s64_2 <- [0]*(XLEN-1) || signbit2
-    RT <- (res1 & m | smask1) + s64_1
-    RS <- (res2 & m | smask2) + s64_2
+    prod1 <- MULS(RB, sum)[XLEN:(XLEN*2)-1]
+    prod2 <- MULS(RB, diff)[XLEN:(XLEN*2)-1]
+    if n = 0 then
+        #round <- EXTS([0]*(XLEN-1) || [1]*1)
+        #prod1 <- ROTL64(prod1, 1)
+        #prod2 <- ROTL64(prod2, 1)
+        #prod1 <- prod1 + round
+        #prod2 <- prod2 + round
+        #res1 <- ROTL64(prod1, XLEN-1)
+        #res2 <- ROTL64(prod2, XLEN-1)
+        #m <- MASK(1, (XLEN-1))
+        RT <- prod1
+        RS <- prod2
+    else
+        round <- EXTS([0]*(XLEN -n -1) || [1]*1 || [0]*(n-1))
+        prod1 <- prod1 + round
+        prod2 <- prod2 + round
+        res1 <- ROTL64(prod1, XLEN-n)
+        res2 <- ROTL64(prod2, XLEN-n)
+        m <- MASK(n, (XLEN-1))
+        signbit1 <- prod1[0]
+        signbit2 <- prod2[0]
+        smask1 <- ([signbit1]*XLEN) & ¬m
+        smask2 <- ([signbit2]*XLEN) & ¬m
+        RT <- (res1 & m | smask1)
+        RS <- (res2 & m | smask2)
 
 Special Registers Altered:
 
diff --git a/src/openpower/test/alu/maddsubrs_cases.py b/src/openpower/test/alu/maddsubrs_cases.py
index feace48d..56b61f82 100644
--- a/src/openpower/test/alu/maddsubrs_cases.py
+++ b/src/openpower/test/alu/maddsubrs_cases.py
@@ -17,13 +17,27 @@ class MADDSUBRSTestCase(TestAccumulatorBase):
         lst = list(isa)
 
         initial_regs = [0] * 32
-        initial_regs[1] = 0x00000a70
+        initial_regs[1] = 0x00000a71
         initial_regs[2] = 0x0000e6b8
         initial_regs[3] = 0x00002d41
 
         e = ExpectedState(pc=4)
-        e.intregs[1] = 0x0000aa85
+        e.intregs[1] = 0x0000aa86
         e.intregs[2] = 0xffffffffffff643e
         e.intregs[3] = 0x00002d41
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
+    def case_1_maddsubrs(self):
+        isa = SVP64Asm(["maddsubrs 1,2,0,3"])
+        lst = list(isa)
+
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x00000a71
+        initial_regs[2] = 0x0000e6b8
+        initial_regs[3] = 0x00002d41
+
+        e = ExpectedState(pc=4)
+        e.intregs[1] = 0x2aa17069
+        e.intregs[2] = 0xffffffffd90f96f9
+        e.intregs[3] = 0x00002d41
+        self.add_case(Program(lst, bigendian), initial_regs, expected=e)
-- 
2.30.2