From 735a77784244d677a1ee33978f9e1aad48e7edae Mon Sep 17 00:00:00 2001 From: Anuj Phogat Date: Mon, 4 Nov 2013 14:48:51 -0800 Subject: [PATCH] i965: Fix 'SIMD16 only' dispatch of fragment shader in case of sample shading This patch make changes to correctly set up the Dispatch GRF Start Register in case of 'SIMD16 only' FS dispatch. This fixes an issue of incorrect rendering on dolphin emulator with GL_SAMPLE_SHADING enabled. Signed-off-by: Anuj Phogat Reviewed-by: Eric Anholt --- src/mesa/drivers/dri/i965/gen6_wm_state.c | 20 +++++++++++++------- src/mesa/drivers/dri/i965/gen7_wm_state.c | 19 ++++++++++++------- 2 files changed, 25 insertions(+), 14 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c index 3f9f8f4bf37..83a17083608 100644 --- a/src/mesa/drivers/dri/i965/gen6_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c @@ -151,11 +151,6 @@ upload_wm_state(struct brw_context *brw) dw2 |= ((brw->wm.prog_data->base.binding_table.size_bytes / 4) << GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT); - dw4 |= (brw->wm.prog_data->first_curbe_grf << - GEN6_WM_DISPATCH_START_GRF_SHIFT_0); - dw4 |= (brw->wm.prog_data->first_curbe_grf_16 << - GEN6_WM_DISPATCH_START_GRF_SHIFT_2); - dw5 |= (brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT; /* CACHE_NEW_WM_PROG */ @@ -171,11 +166,22 @@ upload_wm_state(struct brw_context *brw) if (brw->wm.prog_data->prog_offset_16) { dw5 |= GEN6_WM_16_DISPATCH_ENABLE; - if (min_inv_per_frag == 1) + + if (min_inv_per_frag == 1) { dw5 |= GEN6_WM_8_DISPATCH_ENABLE; + dw4 |= (brw->wm.prog_data->first_curbe_grf << + GEN6_WM_DISPATCH_START_GRF_SHIFT_0); + dw4 |= (brw->wm.prog_data->first_curbe_grf_16 << + GEN6_WM_DISPATCH_START_GRF_SHIFT_2); + } else + dw4 |= (brw->wm.prog_data->first_curbe_grf_16 << + GEN6_WM_DISPATCH_START_GRF_SHIFT_0); } - else + else { dw5 |= GEN6_WM_8_DISPATCH_ENABLE; + dw4 |= (brw->wm.prog_data->first_curbe_grf << + GEN6_WM_DISPATCH_START_GRF_SHIFT_0); + } /* CACHE_NEW_WM_PROG | _NEW_COLOR */ if (brw->wm.prog_data->dual_src_blend && diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c index 531b1a4c9cd..65c9bbf2ba1 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c @@ -234,16 +234,21 @@ upload_ps_state(struct brw_context *brw) if (brw->wm.prog_data->prog_offset_16) { dw4 |= GEN7_PS_16_DISPATCH_ENABLE; - if (min_inv_per_frag == 1) + if (min_inv_per_frag == 1) { dw4 |= GEN7_PS_8_DISPATCH_ENABLE; + dw5 |= (brw->wm.prog_data->first_curbe_grf << + GEN7_PS_DISPATCH_START_GRF_SHIFT_0); + dw5 |= (brw->wm.prog_data->first_curbe_grf_16 << + GEN7_PS_DISPATCH_START_GRF_SHIFT_2); + } else + dw5 |= (brw->wm.prog_data->first_curbe_grf_16 << + GEN7_PS_DISPATCH_START_GRF_SHIFT_0); } - else + else { dw4 |= GEN7_PS_8_DISPATCH_ENABLE; - - dw5 |= (brw->wm.prog_data->first_curbe_grf << - GEN7_PS_DISPATCH_START_GRF_SHIFT_0); - dw5 |= (brw->wm.prog_data->first_curbe_grf_16 << - GEN7_PS_DISPATCH_START_GRF_SHIFT_2); + dw5 |= (brw->wm.prog_data->first_curbe_grf << + GEN7_PS_DISPATCH_START_GRF_SHIFT_0); + } BEGIN_BATCH(8); OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2)); -- 2.30.2