From 736b7c87a60181ba6c761ddcf1b70487bcb80e41 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 4 Jun 2020 13:48:17 +0100 Subject: [PATCH] use copy of FHDLTestCase --- src/soc/decoder/formal/proof_decoder.py | 2 +- src/soc/decoder/formal/proof_decoder2.py | 2 +- src/soc/decoder/isa/test_caller.py | 2 +- src/soc/decoder/test/test_decoder_gas.py | 2 +- src/soc/decoder/test/test_power_decoder.py | 2 +- src/soc/experiment/proof_datamerger.py | 2 +- src/soc/fu/alu/formal/proof_input_stage.py | 2 +- src/soc/fu/alu/formal/proof_main_stage.py | 2 +- src/soc/fu/alu/formal/proof_output_stage.py | 2 +- src/soc/fu/alu/test/test_pipe_caller.py | 2 +- src/soc/fu/branch/formal/proof_input_stage.py | 2 +- src/soc/fu/branch/formal/proof_main_stage.py | 2 +- src/soc/fu/branch/test/test_pipe_caller.py | 2 +- src/soc/fu/compunits/formal/proof_fu.py | 2 +- src/soc/fu/compunits/formal/test_compunit.py | 2 +- src/soc/fu/compunits/test/test_compunit.py | 2 +- src/soc/fu/cr/formal/proof_main_stage.py | 2 +- src/soc/fu/cr/test/test_pipe_caller.py | 2 +- src/soc/fu/div/formal/proof_main_stage.py | 2 +- src/soc/fu/div/test/test_pipe_caller.py | 2 +- src/soc/fu/logical/formal/proof_bpermd.py | 2 +- src/soc/fu/logical/formal/proof_input_stage.py | 2 +- src/soc/fu/logical/formal/proof_main_stage.py | 2 +- src/soc/fu/logical/test/test_countzero.py | 2 +- src/soc/fu/logical/test/test_pipe_caller.py | 2 +- src/soc/fu/mul/formal/proof_main_stage.py | 2 +- src/soc/fu/mul/test/test_pipe_caller.py | 2 +- src/soc/fu/shift_rot/formal/proof_main_stage.py | 2 +- src/soc/fu/shift_rot/test/test_maskgen.py | 2 +- src/soc/fu/shift_rot/test/test_pipe_caller.py | 2 +- src/soc/minerva/test/test_cache.py | 2 +- src/soc/regfile/formal/proof_regfile.py | 2 +- src/soc/regfile/formal/proof_regfile_array.py | 2 +- src/soc/regfile/formal/proof_regfile_binary.py | 2 +- 34 files changed, 34 insertions(+), 34 deletions(-) diff --git a/src/soc/decoder/formal/proof_decoder.py b/src/soc/decoder/formal/proof_decoder.py index 6aa1bc14..e1d793ea 100644 --- a/src/soc/decoder/formal/proof_decoder.py +++ b/src/soc/decoder/formal/proof_decoder.py @@ -1,6 +1,6 @@ from nmigen import Module, Signal, Elaboratable, Cat from nmigen.asserts import Assert, AnyConst, Assume -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from soc.decoder.power_decoder import create_pdecode, PowerOp from soc.decoder.power_enums import (In1Sel, In2Sel, In3Sel, diff --git a/src/soc/decoder/formal/proof_decoder2.py b/src/soc/decoder/formal/proof_decoder2.py index 981a4d22..d36ec447 100644 --- a/src/soc/decoder/formal/proof_decoder2.py +++ b/src/soc/decoder/formal/proof_decoder2.py @@ -1,6 +1,6 @@ from nmigen import Module, Signal, Elaboratable, Cat, Repl from nmigen.asserts import Assert, AnyConst -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from soc.decoder.power_decoder import create_pdecode, PowerOp from soc.decoder.power_enums import (In1Sel, In2Sel, In3Sel, diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py index ea2bca9e..b4689dd6 100644 --- a/src/soc/decoder/isa/test_caller.py +++ b/src/soc/decoder/isa/test_caller.py @@ -1,6 +1,6 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase import unittest from soc.decoder.isa.caller import ISACaller from soc.decoder.power_decoder import (create_pdecode) diff --git a/src/soc/decoder/test/test_decoder_gas.py b/src/soc/decoder/test/test_decoder_gas.py index 08862575..80206db4 100644 --- a/src/soc/decoder/test/test_decoder_gas.py +++ b/src/soc/decoder/test/test_decoder_gas.py @@ -1,6 +1,6 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase import unittest from soc.decoder.power_decoder import (create_pdecode) from soc.decoder.power_enums import (Function, InternalOp, diff --git a/src/soc/decoder/test/test_power_decoder.py b/src/soc/decoder/test/test_power_decoder.py index 6f379836..a03589c3 100644 --- a/src/soc/decoder/test/test_power_decoder.py +++ b/src/soc/decoder/test/test_power_decoder.py @@ -1,6 +1,6 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import os import unittest diff --git a/src/soc/experiment/proof_datamerger.py b/src/soc/experiment/proof_datamerger.py index cfa936e1..6fe7aead 100644 --- a/src/soc/experiment/proof_datamerger.py +++ b/src/soc/experiment/proof_datamerger.py @@ -5,7 +5,7 @@ from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl, signed) from nmigen.asserts import Assert, AnyConst, AnySeq, Assume, Cover -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil from soc.experiment.l0_cache import DataMerger diff --git a/src/soc/fu/alu/formal/proof_input_stage.py b/src/soc/fu/alu/formal/proof_input_stage.py index 53e1dc36..f9b71600 100644 --- a/src/soc/fu/alu/formal/proof_input_stage.py +++ b/src/soc/fu/alu/formal/proof_input_stage.py @@ -3,7 +3,7 @@ from nmigen import Module, Signal, Elaboratable, Mux from nmigen.asserts import Assert, AnyConst, Assume, Cover -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil from soc.fu.alu.input_stage import ALUInputStage diff --git a/src/soc/fu/alu/formal/proof_main_stage.py b/src/soc/fu/alu/formal/proof_main_stage.py index c6682280..c1e71536 100644 --- a/src/soc/fu/alu/formal/proof_main_stage.py +++ b/src/soc/fu/alu/formal/proof_main_stage.py @@ -10,7 +10,7 @@ Links: from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl, signed) from nmigen.asserts import Assert, AnyConst, Assume, Cover -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil from soc.fu.alu.main_stage import ALUMainStage diff --git a/src/soc/fu/alu/formal/proof_output_stage.py b/src/soc/fu/alu/formal/proof_output_stage.py index d76a5e27..8148d1eb 100644 --- a/src/soc/fu/alu/formal/proof_output_stage.py +++ b/src/soc/fu/alu/formal/proof_output_stage.py @@ -9,7 +9,7 @@ Links: from nmigen import Module, Signal, Elaboratable, Mux, Cat, signed from nmigen.asserts import Assert, AnyConst, Assume, Cover -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil from soc.fu.alu.output_stage import ALUOutputStage diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index 50e8e9b1..c6acbae1 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -1,6 +1,6 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest from soc.decoder.isa.caller import ISACaller, special_sprs diff --git a/src/soc/fu/branch/formal/proof_input_stage.py b/src/soc/fu/branch/formal/proof_input_stage.py index 3ac3ac89..0ce65226 100644 --- a/src/soc/fu/branch/formal/proof_input_stage.py +++ b/src/soc/fu/branch/formal/proof_input_stage.py @@ -3,7 +3,7 @@ from nmigen import Module, Signal, Elaboratable, Mux from nmigen.asserts import Assert, AnyConst, Assume, Cover -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil from soc.fu.alu.input_stage import ALUInputStage diff --git a/src/soc/fu/branch/formal/proof_main_stage.py b/src/soc/fu/branch/formal/proof_main_stage.py index 32a29651..7a94c1d3 100644 --- a/src/soc/fu/branch/formal/proof_main_stage.py +++ b/src/soc/fu/branch/formal/proof_main_stage.py @@ -9,7 +9,7 @@ Links: from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl, signed, Array) from nmigen.asserts import Assert, AnyConst, Assume, Cover -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmutil.extend import exts from nmigen.cli import rtlil diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py index 924a5083..5388e13b 100644 --- a/src/soc/fu/branch/test/test_pipe_caller.py +++ b/src/soc/fu/branch/test/test_pipe_caller.py @@ -1,6 +1,6 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest from soc.decoder.isa.caller import ISACaller, special_sprs diff --git a/src/soc/fu/compunits/formal/proof_fu.py b/src/soc/fu/compunits/formal/proof_fu.py index c9ecd623..56c75b7b 100644 --- a/src/soc/fu/compunits/formal/proof_fu.py +++ b/src/soc/fu/compunits/formal/proof_fu.py @@ -8,7 +8,7 @@ from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl, signed, ResetSignal) from nmigen.asserts import (Assert, AnyConst, Assume, Cover, Initial, Rose, Fell, Stable, Past) -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest diff --git a/src/soc/fu/compunits/formal/test_compunit.py b/src/soc/fu/compunits/formal/test_compunit.py index 2e6850aa..956b5d77 100644 --- a/src/soc/fu/compunits/formal/test_compunit.py +++ b/src/soc/fu/compunits/formal/test_compunit.py @@ -1,6 +1,6 @@ from nmigen import Signal, Module from nmigen.back.pysim import Simulator, Delay, Settle -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil from soc.fu.compunits.compunits import FunctionUnitBaseSingle from soc.experiment.alu_hier import DummyALU diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py index c4596cef..293a5ef7 100644 --- a/src/soc/fu/compunits/test/test_compunit.py +++ b/src/soc/fu/compunits/test/test_compunit.py @@ -1,6 +1,6 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest from soc.decoder.isa.caller import ISACaller, special_sprs diff --git a/src/soc/fu/cr/formal/proof_main_stage.py b/src/soc/fu/cr/formal/proof_main_stage.py index 0bf37299..96dbe4bf 100644 --- a/src/soc/fu/cr/formal/proof_main_stage.py +++ b/src/soc/fu/cr/formal/proof_main_stage.py @@ -8,7 +8,7 @@ Links: from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl, signed, Array) from nmigen.asserts import Assert, AnyConst, Assume, Cover -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil from soc.fu.cr.main_stage import CRMainStage diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py index b67ed831..6f6fd2d3 100644 --- a/src/soc/fu/cr/test/test_pipe_caller.py +++ b/src/soc/fu/cr/test/test_pipe_caller.py @@ -1,6 +1,6 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest from soc.decoder.isa.caller import ISACaller, special_sprs diff --git a/src/soc/fu/div/formal/proof_main_stage.py b/src/soc/fu/div/formal/proof_main_stage.py index 456ff815..f3baa1b6 100644 --- a/src/soc/fu/div/formal/proof_main_stage.py +++ b/src/soc/fu/div/formal/proof_main_stage.py @@ -9,7 +9,7 @@ Links: from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl, signed) from nmigen.asserts import Assert, AnyConst, Assume, Cover -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.lib.coding import PriorityEncoder from nmigen.cli import rtlil diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py index a9be3695..3b58490d 100644 --- a/src/soc/fu/div/test/test_pipe_caller.py +++ b/src/soc/fu/div/test/test_pipe_caller.py @@ -1,6 +1,6 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest from soc.decoder.isa.caller import ISACaller, special_sprs diff --git a/src/soc/fu/logical/formal/proof_bpermd.py b/src/soc/fu/logical/formal/proof_bpermd.py index e987f88b..02f65442 100644 --- a/src/soc/fu/logical/formal/proof_bpermd.py +++ b/src/soc/fu/logical/formal/proof_bpermd.py @@ -4,7 +4,7 @@ from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl, signed) from nmigen.asserts import Assert, AnyConst, Assume, Cover -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil from soc.fu.logical.bpermd import Bpermd diff --git a/src/soc/fu/logical/formal/proof_input_stage.py b/src/soc/fu/logical/formal/proof_input_stage.py index c80b6fb3..16f3df04 100644 --- a/src/soc/fu/logical/formal/proof_input_stage.py +++ b/src/soc/fu/logical/formal/proof_input_stage.py @@ -3,7 +3,7 @@ from nmigen import Module, Signal, Elaboratable, Mux from nmigen.asserts import Assert, AnyConst, Assume, Cover -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil from soc.fu.alu.input_stage import ALUInputStage diff --git a/src/soc/fu/logical/formal/proof_main_stage.py b/src/soc/fu/logical/formal/proof_main_stage.py index 6cb31ead..de1c788d 100644 --- a/src/soc/fu/logical/formal/proof_main_stage.py +++ b/src/soc/fu/logical/formal/proof_main_stage.py @@ -9,7 +9,7 @@ Links: from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl, signed) from nmigen.asserts import Assert, AnyConst, Assume, Cover -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.lib.coding import PriorityEncoder from nmigen.cli import rtlil diff --git a/src/soc/fu/logical/test/test_countzero.py b/src/soc/fu/logical/test/test_countzero.py index 43aae01d..3a78fd8f 100644 --- a/src/soc/fu/logical/test/test_countzero.py +++ b/src/soc/fu/logical/test/test_countzero.py @@ -2,7 +2,7 @@ from nmigen import Module, Signal from nmigen.cli import rtlil from nmigen.back.pysim import Simulator, Delay -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase import unittest from soc.fu.logical.countzero import ZeroCounter diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py index 480603ab..f64ea531 100644 --- a/src/soc/fu/logical/test/test_pipe_caller.py +++ b/src/soc/fu/logical/test/test_pipe_caller.py @@ -1,6 +1,6 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest from soc.decoder.isa.caller import ISACaller, special_sprs diff --git a/src/soc/fu/mul/formal/proof_main_stage.py b/src/soc/fu/mul/formal/proof_main_stage.py index afcf12e7..0e44e5e8 100644 --- a/src/soc/fu/mul/formal/proof_main_stage.py +++ b/src/soc/fu/mul/formal/proof_main_stage.py @@ -4,7 +4,7 @@ from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl, signed) from nmigen.asserts import Assert, AnyConst, Assume, Cover -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil from soc.fu.shift_rot.main_stage import ShiftRotMainStage diff --git a/src/soc/fu/mul/test/test_pipe_caller.py b/src/soc/fu/mul/test/test_pipe_caller.py index 2a13a4cd..88ac5499 100644 --- a/src/soc/fu/mul/test/test_pipe_caller.py +++ b/src/soc/fu/mul/test/test_pipe_caller.py @@ -1,6 +1,6 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest from soc.decoder.isa.caller import ISACaller, special_sprs diff --git a/src/soc/fu/shift_rot/formal/proof_main_stage.py b/src/soc/fu/shift_rot/formal/proof_main_stage.py index 968eecdd..9b083a54 100644 --- a/src/soc/fu/shift_rot/formal/proof_main_stage.py +++ b/src/soc/fu/shift_rot/formal/proof_main_stage.py @@ -8,7 +8,7 @@ Links: from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl, signed) from nmigen.asserts import Assert, AnyConst, Assume, Cover -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil from soc.fu.shift_rot.main_stage import ShiftRotMainStage diff --git a/src/soc/fu/shift_rot/test/test_maskgen.py b/src/soc/fu/shift_rot/test/test_maskgen.py index 5c7c2941..385899d1 100644 --- a/src/soc/fu/shift_rot/test/test_maskgen.py +++ b/src/soc/fu/shift_rot/test/test_maskgen.py @@ -1,6 +1,6 @@ from nmigen import Signal, Module from nmigen.back.pysim import Simulator, Delay, Settle -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil from soc.fu.shift_rot.maskgen import MaskGen from soc.decoder.helpers import MASK diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py index db441696..f73f9b23 100644 --- a/src/soc/fu/shift_rot/test/test_pipe_caller.py +++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py @@ -1,6 +1,6 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest from soc.decoder.isa.caller import ISACaller, special_sprs diff --git a/src/soc/minerva/test/test_cache.py b/src/soc/minerva/test/test_cache.py index e52f034a..c56a465d 100644 --- a/src/soc/minerva/test/test_cache.py +++ b/src/soc/minerva/test/test_cache.py @@ -1,6 +1,6 @@ from nmigen import * from nmigen.utils import log2_int -from nmigen.test.utils import * +from nmutil.formaltest import * from nmigen.asserts import * from ..cache import L1Cache diff --git a/src/soc/regfile/formal/proof_regfile.py b/src/soc/regfile/formal/proof_regfile.py index 6dc89144..b988ad32 100644 --- a/src/soc/regfile/formal/proof_regfile.py +++ b/src/soc/regfile/formal/proof_regfile.py @@ -4,7 +4,7 @@ from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl, signed, ResetSignal) from nmigen.asserts import (Assert, AnySeq, Assume, Cover, Initial, Rose, Fell, Stable, Past) -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest diff --git a/src/soc/regfile/formal/proof_regfile_array.py b/src/soc/regfile/formal/proof_regfile_array.py index b35c51eb..fc7c293c 100644 --- a/src/soc/regfile/formal/proof_regfile_array.py +++ b/src/soc/regfile/formal/proof_regfile_array.py @@ -4,7 +4,7 @@ from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl, signed, ResetSignal, Array) from nmigen.asserts import (Assert, AnySeq, Assume, Cover, Initial, Rose, Fell, Stable, Past) -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest diff --git a/src/soc/regfile/formal/proof_regfile_binary.py b/src/soc/regfile/formal/proof_regfile_binary.py index d47453a0..1ae6b73c 100644 --- a/src/soc/regfile/formal/proof_regfile_binary.py +++ b/src/soc/regfile/formal/proof_regfile_binary.py @@ -4,7 +4,7 @@ from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl, signed, ResetSignal, Array) from nmigen.asserts import (Assert, AnySeq, Assume, Cover, Initial, Rose, Fell, Stable, Past) -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest import math -- 2.30.2