From 73aa7f9467052bbc2e261c5715426a9a93e799a7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 13 Aug 2020 15:46:58 +0100 Subject: [PATCH] remove latchregister, sync src oper_i into MultiCompUnit --- src/soc/experiment/compalu_multi.py | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py index d4d7c60a..8db244a1 100644 --- a/src/soc/experiment/compalu_multi.py +++ b/src/soc/experiment/compalu_multi.py @@ -252,9 +252,10 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): m.d.comb += req_l.s.eq(alu_pulsem & self.wrmask) m.d.sync += req_l.r.eq(reset_w | prev_wr_go) - # create a latch/register for the operand - oper_r = self.opsubsetkls(name="oper_r") - latchregister(m, self.oper_i, oper_r, self.issue_i, "oper_l") + # pass operation to the ALU (sync: plenty time to wait for src reads) + op = self.get_op() + with m.If(self.issue_i): + m.d.sync += op.eq(self.oper_i) # and for each output from the ALU: capture when ALU output is valid drl = [] @@ -282,10 +283,6 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): # a regfile port because this particular output is not valid" m.d.comb += self.wrmask.eq(Cat(*wrok)) - # pass operation to the ALU (sync: plenty time to wait for src reads) - op = self.get_op() - m.d.sync += op.eq(oper_r) - # create list of src/alu-src/src-latch. override 1st and 2nd one below. # in the case, for ALU and Logical pipelines, we assume RB is the # 2nd operand in the input "regspec". see for example -- 2.30.2