From 73b50707b549ba275509592aad33019290515019 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 12 Nov 2020 21:54:10 +0000 Subject: [PATCH] remove niolib io_in/out signal, no longer needed --- experiments9/doDesign.py | 6 +----- experiments9/non_generated/ls180.vst | 14 -------------- 2 files changed, 1 insertion(+), 19 deletions(-) diff --git a/experiments9/doDesign.py b/experiments9/doDesign.py index 16f794c..2841a4c 100644 --- a/experiments9/doDesign.py +++ b/experiments9/doDesign.py @@ -107,11 +107,7 @@ def generate_spec(): # where direction is "+" for out, "-" for in, "*" for bi-directionaly if len(pad) == 4: print("4-long io", pad) - if pad[-1] == '-': - en_sig = 'io_in' - if pad[-1] == '+': - en_sig = 'io_out' - padspec = [padside, None, padname, pad[1], pad[2], en_sig] + padspec = [padside, None, padname, pad[1], pad[2]] # format here is: # ['padname', 'something', 'to core', 'from core', 'en', 'direction'] diff --git a/experiments9/non_generated/ls180.vst b/experiments9/non_generated/ls180.vst index e4d51e8..9e24a4b 100644 --- a/experiments9/non_generated/ls180.vst +++ b/experiments9/non_generated/ls180.vst @@ -59,8 +59,6 @@ entity ls180 is ; gpio_o : out bit_vector(15 downto 0) ; gpio_oe : out bit_vector(15 downto 0) ; sdram_dq_o : out bit_vector(15 downto 0) - ; io_in : out bit - ; io_out : out bit ; vdd : linkage bit ; vss : linkage bit ); @@ -92,23 +90,11 @@ architecture structural of ls180 is begin - zero_1 : zero_x0 - port map ( nq => io_in - , vdd => vdd - , vss => vss - ); - zero_0 : zero_x0 port map ( nq => i2c_scl , vdd => vdd , vss => vss ); - one_0 : one_x0 - port map ( q => io_out - , vdd => vdd - , vss => vss - ); - end structural; -- 2.30.2