From 73c497e4d0235120c686249b197472b1c40a99f3 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sat, 20 Nov 2021 14:44:23 +0000
Subject: [PATCH]

---
 3d_gpu/architecture/regfile.mdwn | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn
index 7a5339070..3aa7ba12c 100644
--- a/3d_gpu/architecture/regfile.mdwn
+++ b/3d_gpu/architecture/regfile.mdwn
@@ -19,6 +19,11 @@ Source code:
 
 For a GPU, the FP and Integer registers need to be a massive 128 x 64-bit.
 
+Video walkthrough of regfile relationship to Function Units in core:
+<https://youtu.be/7Th1b-jq40k>
+
+[[!img core_regfiles_fus_pickers.jpg size="500px"]]
+
 # Regfile groups, Port Allocations and bit-widths
 
 * INT regfile: 32x 64-bit with 4R1W
-- 
2.30.2