From 73cfab8b234c595e86413d4f7169bddc1a1184dd Mon Sep 17 00:00:00 2001
From: Korey Sewell <ksewell@umich.edu>
Date: Sun, 19 Jun 2011 21:43:35 -0400
Subject: [PATCH] inorder: DynInst handling of stores for big-endian ISAs The
 DynInst was not performing the host-to-guest translation which ended up
 breaking stores for SPARC

---
 src/cpu/inorder/inorder_dyn_inst.cc     | 13 ++++++++-----
 src/cpu/inorder/resources/cache_unit.cc |  6 ++++++
 2 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index dea1a7dfe..1bbd4f639 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -527,7 +527,10 @@ InOrderDynInst::read(Addr addr, T &data, unsigned flags)
         traceData->setData(data);
     }
     Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
+    DPRINTF(InOrderDynInst, "[sn:%i] (1) Received Bytes %x\n", seqNum, data);
     data = TheISA::gtoh(data);
+    DPRINTF(InOrderDynInst, "[sn%:i] (2) Received Bytes %x\n", seqNum, data);
+
     if (traceData)
         traceData->setData(data);
     return fault;
@@ -588,6 +591,8 @@ InOrderDynInst::writeBytes(uint8_t *data, unsigned size,
 {
     assert(sizeof(storeData) >= size);
     memcpy(&storeData, data, size);
+    DPRINTF(InOrderDynInst, "(2) [tid:%i]: [sn:%i] Setting store data to %#x.\n",
+            threadNumber, seqNum, storeData);
     return cpu->write(this, (uint8_t *)&storeData, size, addr, flags, res);
 }
 
@@ -595,15 +600,13 @@ template<class T>
 inline Fault
 InOrderDynInst::write(T data, Addr addr, unsigned flags, uint64_t *res)
 {
-    storeData  = data;
-
-    DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting store data to %#x.\n",
-            threadNumber, seqNum, storeData);
     if (traceData) {
         traceData->setAddr(addr);
         traceData->setData(data);
     }
-    storeData = TheISA::htog(data);
+    data = TheISA::htog(data);
+    DPRINTF(InOrderDynInst, "(1) [tid:%i]: [sn:%i] Setting store data to %#x.\n",
+            threadNumber, seqNum, data);
     return writeBytes((uint8_t*)&data, sizeof(T), addr, flags, res);
 }
 
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index c38e5541d..c1a3590be 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -840,6 +840,12 @@ CacheUnit::doCacheAccess(DynInstPtr inst, uint64_t *write_res,
         } else {
             cache_req->dataPkt->dataStatic(&cache_req->inst->storeData);            
         }
+
+        DPRINTF(InOrderCachePort,
+                "[tid:%u]: [sn:%i]: Storing data: %s\n",
+                tid, inst->seqNum,
+                printMemData(cache_req->dataPkt->getPtr<uint8_t>(),
+                             cache_req->dataPkt->getSize()));
         
         if (cache_req->memReq->isCondSwap()) {
             assert(write_res);
-- 
2.30.2