From 73e3da51639120db26eff9bf39e2339d92a44488 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Mon, 6 Nov 2017 20:02:27 +0000 Subject: [PATCH] [AArch64] Pass number of units to aarch64_reverse_mask This patch passes the number of units to aarch64_reverse_mask, which avoids a to_constant () once GET_MODE_NUNITS is variable. 2017-11-06 Richard Sandiford Alan Hayward David Sherwood gcc/ * config/aarch64/aarch64-protos.h (aarch64_reverse_mask): Take the number of units too. * config/aarch64/aarch64.c (aarch64_reverse_mask): Likewise. * config/aarch64/aarch64-simd.md (vec_load_lanesoi) (vec_store_lanesoi, vec_load_lanesci) (vec_store_lanesci, vec_load_lanesxi) (vec_store_lanesxi): Update accordingly. Reviewed-by: James Greenhalgh Co-Authored-By: Alan Hayward Co-Authored-By: David Sherwood From-SVN: r254467 --- gcc/ChangeLog | 12 ++++++++++++ gcc/config/aarch64/aarch64-protos.h | 2 +- gcc/config/aarch64/aarch64-simd.md | 12 ++++++------ gcc/config/aarch64/aarch64.c | 10 ++++++---- 4 files changed, 25 insertions(+), 11 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 04f4d13d271..ad78a257288 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2017-11-06 Richard Sandiford + Alan Hayward + David Sherwood + + * config/aarch64/aarch64-protos.h (aarch64_reverse_mask): Take + the number of units too. + * config/aarch64/aarch64.c (aarch64_reverse_mask): Likewise. + * config/aarch64/aarch64-simd.md (vec_load_lanesoi) + (vec_store_lanesoi, vec_load_lanesci) + (vec_store_lanesci, vec_load_lanesxi) + (vec_store_lanesxi): Update accordingly. + 2017-11-06 Richard Sandiford Alan Hayward David Sherwood diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 4df2ee00f8f..39691155aff 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -352,7 +352,7 @@ bool aarch64_mask_and_shift_for_ubfiz_p (scalar_int_mode, rtx, rtx); bool aarch64_zero_extend_const_eq (machine_mode, rtx, machine_mode, rtx); bool aarch64_move_imm (HOST_WIDE_INT, machine_mode); bool aarch64_mov_operand_p (rtx, machine_mode); -rtx aarch64_reverse_mask (machine_mode); +rtx aarch64_reverse_mask (machine_mode, unsigned int); bool aarch64_offset_7bit_signed_scaled_p (machine_mode, HOST_WIDE_INT); char *aarch64_output_scalar_simd_mov_immediate (rtx, scalar_int_mode); char *aarch64_output_simd_mov_immediate (rtx, machine_mode, unsigned, diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 445503d8449..642f4b1bfa3 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4633,7 +4633,7 @@ if (BYTES_BIG_ENDIAN) { rtx tmp = gen_reg_rtx (OImode); - rtx mask = aarch64_reverse_mask (mode); + rtx mask = aarch64_reverse_mask (mode, ); emit_insn (gen_aarch64_simd_ld2 (tmp, operands[1])); emit_insn (gen_aarch64_rev_reglistoi (operands[0], tmp, mask)); } @@ -4677,7 +4677,7 @@ if (BYTES_BIG_ENDIAN) { rtx tmp = gen_reg_rtx (OImode); - rtx mask = aarch64_reverse_mask (mode); + rtx mask = aarch64_reverse_mask (mode, ); emit_insn (gen_aarch64_rev_reglistoi (tmp, operands[1], mask)); emit_insn (gen_aarch64_simd_st2 (operands[0], tmp)); } @@ -4731,7 +4731,7 @@ if (BYTES_BIG_ENDIAN) { rtx tmp = gen_reg_rtx (CImode); - rtx mask = aarch64_reverse_mask (mode); + rtx mask = aarch64_reverse_mask (mode, ); emit_insn (gen_aarch64_simd_ld3 (tmp, operands[1])); emit_insn (gen_aarch64_rev_reglistci (operands[0], tmp, mask)); } @@ -4775,7 +4775,7 @@ if (BYTES_BIG_ENDIAN) { rtx tmp = gen_reg_rtx (CImode); - rtx mask = aarch64_reverse_mask (mode); + rtx mask = aarch64_reverse_mask (mode, ); emit_insn (gen_aarch64_rev_reglistci (tmp, operands[1], mask)); emit_insn (gen_aarch64_simd_st3 (operands[0], tmp)); } @@ -4829,7 +4829,7 @@ if (BYTES_BIG_ENDIAN) { rtx tmp = gen_reg_rtx (XImode); - rtx mask = aarch64_reverse_mask (mode); + rtx mask = aarch64_reverse_mask (mode, ); emit_insn (gen_aarch64_simd_ld4 (tmp, operands[1])); emit_insn (gen_aarch64_rev_reglistxi (operands[0], tmp, mask)); } @@ -4873,7 +4873,7 @@ if (BYTES_BIG_ENDIAN) { rtx tmp = gen_reg_rtx (XImode); - rtx mask = aarch64_reverse_mask (mode); + rtx mask = aarch64_reverse_mask (mode, ); emit_insn (gen_aarch64_rev_reglistxi (tmp, operands[1], mask)); emit_insn (gen_aarch64_simd_st4 (operands[0], tmp)); } diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index ffcca32cd3c..b3ce7f6d271 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -13699,16 +13699,18 @@ aarch64_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel) return ret; } +/* Generate a byte permute mask for a register of mode MODE, + which has NUNITS units. */ + rtx -aarch64_reverse_mask (machine_mode mode) +aarch64_reverse_mask (machine_mode mode, unsigned int nunits) { /* We have to reverse each vector because we dont have a permuted load that can reverse-load according to ABI rules. */ rtx mask; rtvec v = rtvec_alloc (16); - int i, j; - int nunits = GET_MODE_NUNITS (mode); - int usize = GET_MODE_UNIT_SIZE (mode); + unsigned int i, j; + unsigned int usize = GET_MODE_UNIT_SIZE (mode); gcc_assert (BYTES_BIG_ENDIAN); gcc_assert (AARCH64_VALID_SIMD_QREG_MODE (mode)); -- 2.30.2