From 73f930e2974d5c674e436cf8bc79f6984c94a35b Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 18 Sep 2022 18:28:50 +0100
Subject: [PATCH] add comments (links to URLs) into power_insns.py for RM modes

---
 src/openpower/decoder/power_insn.py | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index c54c5ca0..1dc99c4c 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1298,6 +1298,10 @@ class BaseRM(_Mapping):
                 yield f"{indent}{', '.join(map(str, members))}"
 
 
+# ********************
+# Normal mode
+# https://libre-soc.org/openpower/sv/normal/
+
 class NormalLDSTBaseRM(BaseRM):
     def specifiers(self, record):
         widths = {
@@ -1461,6 +1465,10 @@ class NormalRM(NormalBaseRM):
     prrc0: NormalPredResultRc0RM
 
 
+# ********************
+# LD/ST Immediate mode
+# https://libre-soc.org/openpower/sv/ldst/
+
 class LDSTImmBaseRM(NormalLDSTBaseRM):
     pass
 
@@ -1551,6 +1559,10 @@ class LDSTImmRM(LDSTImmBaseRM):
     prrc0: LDSTImmPredResultRc0RM
 
 
+# ********************
+# LD/ST Indexed mode
+# https://libre-soc.org/openpower/sv/ldst/
+
 class LDSTIdxBaseRM(NormalLDSTBaseRM):
     pass
 
@@ -1636,6 +1648,11 @@ class LDSTIdxRM(LDSTIdxBaseRM):
     prrc0: LDSTIdxPredResultRc0RM
 
 
+
+# ********************
+# CR ops mode
+# https://libre-soc.org/openpower/sv/cr_ops/
+
 class CROpBaseRM(BaseRM):
     pass
 
@@ -1730,6 +1747,11 @@ class CROpRM(CROpBaseRM):
     ff5: CROpFailFirst5RM
 
 
+# ********************
+# Branches mode
+# https://libre-soc.org/openpower/sv/branches/
+
+
 class BranchBaseRM(BaseRM):
     ALL: BaseRM[4]
     SNZ: BaseRM[5]
-- 
2.30.2