From 740c1ed77c11b4be66c3c3c56660e11f01a383d8 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Fri, 7 Dec 2018 15:01:47 +0000 Subject: [PATCH] [AArch64][SVE] Remove unnecessary PTRUEs from FP arithmetic When using the unpredicated all-register forms of FADD, FSUB and FMUL, the rtl patterns would still have the predicate operand we created for the other forms. This patch splits the patterns after reload in order to get rid of the predicate, like we already do for WHILE. 2018-12-07 Richard Sandiford gcc/ * config/aarch64/iterators.md (SVE_UNPRED_FP_BINARY): New code iterator. (sve_fp_op): Handle minus and mult. * config/aarch64/aarch64-sve.md (*add3, *sub3) (*mul3): Split the patterns after reload if we don't need the predicate operand. (*post_ra_3): New pattern. gcc/testsuite/ * gcc.target/aarch64/sve/pred_elim_1.c: New test. From-SVN: r266891 --- gcc/ChangeLog | 10 +++++ gcc/config/aarch64/aarch64-sve.md | 39 ++++++++++++++++--- gcc/config/aarch64/iterators.md | 5 +++ gcc/testsuite/ChangeLog | 4 ++ .../gcc.target/aarch64/sve/pred_elim_1.c | 23 +++++++++++ 5 files changed, 75 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pred_elim_1.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index dbe8b5f90d9..d1a40254232 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2018-12-07 Richard Sandiford + + * config/aarch64/iterators.md (SVE_UNPRED_FP_BINARY): New code + iterator. + (sve_fp_op): Handle minus and mult. + * config/aarch64/aarch64-sve.md (*add3, *sub3) + (*mul3): Split the patterns after reload if we don't + need the predicate operand. + (*post_ra_3): New pattern. + 2018-12-07 Bin Cheng * profile-count.h (profile_count::oeprator>=): Fix typo by inverting diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 5cd591b9433..edc6cff8fbd 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -2194,7 +2194,7 @@ ) ;; Floating-point addition predicated with a PTRUE. -(define_insn "*add3" +(define_insn_and_split "*add3" [(set (match_operand:SVE_F 0 "register_operand" "=w, w, w") (unspec:SVE_F [(match_operand: 1 "register_operand" "Upl, Upl, Upl") @@ -2206,7 +2206,12 @@ "@ fadd\t%0., %1/m, %0., #%3 fsub\t%0., %1/m, %0., #%N3 - fadd\t%0., %2., %3." + #" + ; Split the unpredicated form after reload, so that we don't have + ; the unnecessary PTRUE. + "&& reload_completed + && register_operand (operands[3], mode)" + [(set (match_dup 0) (plus:SVE_F (match_dup 2) (match_dup 3)))] ) ;; Unpredicated floating-point subtraction. @@ -2225,7 +2230,7 @@ ) ;; Floating-point subtraction predicated with a PTRUE. -(define_insn "*sub3" +(define_insn_and_split "*sub3" [(set (match_operand:SVE_F 0 "register_operand" "=w, w, w, w") (unspec:SVE_F [(match_operand: 1 "register_operand" "Upl, Upl, Upl, Upl") @@ -2240,7 +2245,13 @@ fsub\t%0., %1/m, %0., #%3 fadd\t%0., %1/m, %0., #%N3 fsubr\t%0., %1/m, %0., #%2 - fsub\t%0., %2., %3." + #" + ; Split the unpredicated form after reload, so that we don't have + ; the unnecessary PTRUE. + "&& reload_completed + && register_operand (operands[2], mode) + && register_operand (operands[3], mode)" + [(set (match_dup 0) (minus:SVE_F (match_dup 2) (match_dup 3)))] ) ;; Unpredicated floating-point multiplication. @@ -2259,7 +2270,7 @@ ) ;; Floating-point multiplication predicated with a PTRUE. -(define_insn "*mul3" +(define_insn_and_split "*mul3" [(set (match_operand:SVE_F 0 "register_operand" "=w, w") (unspec:SVE_F [(match_operand: 1 "register_operand" "Upl, Upl") @@ -2270,9 +2281,25 @@ "TARGET_SVE" "@ fmul\t%0., %1/m, %0., #%3 - fmul\t%0., %2., %3." + #" + ; Split the unpredicated form after reload, so that we don't have + ; the unnecessary PTRUE. + "&& reload_completed + && register_operand (operands[3], mode)" + [(set (match_dup 0) (mult:SVE_F (match_dup 2) (match_dup 3)))] ) +;; Unpredicated floating-point binary operations (post-RA only). +;; These are generated by splitting a predicated instruction whose +;; predicate is unused. +(define_insn "*post_ra_3" + [(set (match_operand:SVE_F 0 "register_operand" "=w") + (SVE_UNPRED_FP_BINARY:SVE_F + (match_operand:SVE_F 1 "register_operand" "w") + (match_operand:SVE_F 2 "register_operand" "w")))] + "TARGET_SVE && reload_completed" + "\t%0., %1., %2.") + ;; Unpredicated fma (%0 = (%1 * %2) + %3). (define_expand "fma4" [(set (match_operand:SVE_F 0 "register_operand") diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 524e4e6929b..a80755734d6 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -1220,6 +1220,9 @@ ;; SVE integer binary division operations. (define_code_iterator SVE_INT_BINARY_SD [div udiv]) +;; SVE floating-point operations with an unpredicated all-register form. +(define_code_iterator SVE_UNPRED_FP_BINARY [plus minus mult]) + ;; SVE integer comparisons. (define_code_iterator SVE_INT_CMP [lt le eq ne ge gt ltu leu geu gtu]) @@ -1423,6 +1426,8 @@ ;; The floating-point SVE instruction that implements an rtx code. (define_code_attr sve_fp_op [(plus "fadd") + (minus "fsub") + (mult "fmul") (neg "fneg") (abs "fabs") (sqrt "fsqrt")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 03fc100526f..996cacda1cb 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2018-12-07 Richard Sandiford + + * gcc.target/aarch64/sve/pred_elim_1.c: New test. + 2018-12-07 Rainer Orth * gcc.target/i386/ipa-stack-alignment-2.c: Add diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred_elim_1.c b/gcc/testsuite/gcc.target/aarch64/sve/pred_elim_1.c new file mode 100644 index 00000000000..6b0faf1edef --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred_elim_1.c @@ -0,0 +1,23 @@ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#define TEST_OP(NAME, TYPE, OP) \ + void \ + NAME##_##TYPE (TYPE *restrict a, TYPE *restrict b, \ + TYPE *restrict c, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + a[i] = b[i] OP c[i]; \ + } + +#define TEST_TYPE(TYPE) \ + TEST_OP (add, TYPE, +) \ + TEST_OP (sub, TYPE, -) \ + TEST_OP (mult, TYPE, *) \ + +TEST_TYPE (float) +TEST_TYPE (double) + +/* { dg-final { scan-assembler-times {\tfadd\t} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsub\t} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmul\t} 2 } } */ +/* { dg-final { scan-assembler-not {\tptrue\t} } } */ -- 2.30.2