From 743160d70c1f8f59102bbf90f9548890eab85149 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 5 May 2021 14:02:43 +0100 Subject: [PATCH] add saturate SVP64 RM mode decode --- src/openpower/decoder/power_svp64_rm.py | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/openpower/decoder/power_svp64_rm.py b/src/openpower/decoder/power_svp64_rm.py index 963f2cfb..981e51a8 100644 --- a/src/openpower/decoder/power_svp64_rm.py +++ b/src/openpower/decoder/power_svp64_rm.py @@ -142,6 +142,16 @@ class SVP64RMModeDecode(Elaboratable): comb += self.pred_sz.eq(mode[SVP64MODE.SZ]) comb += self.pred_dz.eq(mode[SVP64MODE.DZ]) + # extract saturate + with m.Switch(mode2): + with m.Case(2): + with m.If(mode[SVP64MODE.N]): + comb += self.saturate.eq(SVP64sat.UNSIGNED) + with m.Else(): + comb += self.saturate.eq(SVP64sat.SIGNED) + with m.Default(): + comb += self.saturate.eq(SVP64sat.NONE) + # extract src/dest predicate. use EXTRA3.MASK because EXTRA2.MASK # is in exactly the same bits srcmask = sel(m, self.rm_in.extra, EXTRA3.MASK) -- 2.30.2