From 74391ca9cc594d592d879c21868241ea6ad587e6 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sun, 7 Mar 2021 12:21:11 +0000
Subject: [PATCH]

---
 openpower/sv/implementation.mdwn | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 94daa39f7..b4d94e589 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -22,12 +22,13 @@ Links:
 
 # Code to convert
 
-There are four projects:
+There are five projects:
 
 * TestIssuer (the HDL)
 * ISACaller (the python-based simulator)
 * power-gem5 (a cycle accurate simulator)
 * Microwatt (VHDL)
+* gcc and binutils
 
 Each of these needs to have SV augmentation, and the best way to
 do it is if they are all done at the same time, implementing the same
@@ -59,7 +60,7 @@ People coordinating different tasks. This doesn't mean exclusive work on these a
 * Cole:
 * Luke: ISACaller, python-assembler-generator-class
 * Tobias:
-* Alexandre: binutils-svp64-assembler
+* Alexandre: binutils-svp64-assembler and gcc
 * Paul: microwatt
 
 # Adding SV
-- 
2.30.2