From 7443f89200f0313ac49c7e437b0d228af1898a62 Mon Sep 17 00:00:00 2001 From: Thomas Watson Date: Mon, 10 May 2021 20:59:34 -0500 Subject: [PATCH] hdl.dsl: raise SyntaxError for mis-nested If/Elif/Else statements --- nmigen/hdl/dsl.py | 5 +++-- tests/test_hdl_dsl.py | 28 ++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/nmigen/hdl/dsl.py b/nmigen/hdl/dsl.py index fd20774..829cd2f 100644 --- a/nmigen/hdl/dsl.py +++ b/nmigen/hdl/dsl.py @@ -226,6 +226,7 @@ class Module(_ModuleBuilderRoot, Elaboratable): cond = self._check_signed_cond(cond) src_loc = tracer.get_src_loc(src_loc_at=1) if_data = self._set_ctrl("If", { + "depth": self.domain._depth, "tests": [], "bodies": [], "src_loc": src_loc, @@ -249,7 +250,7 @@ class Module(_ModuleBuilderRoot, Elaboratable): cond = self._check_signed_cond(cond) src_loc = tracer.get_src_loc(src_loc_at=1) if_data = self._get_ctrl("If") - if if_data is None or len(if_data["tests"]) == 0: + if if_data is None or if_data["depth"] != self.domain._depth: raise SyntaxError("Elif without preceding If") try: _outer_case, self._statements = self._statements, [] @@ -268,7 +269,7 @@ class Module(_ModuleBuilderRoot, Elaboratable): self._check_context("Else", context=None) src_loc = tracer.get_src_loc(src_loc_at=1) if_data = self._get_ctrl("If") - if if_data is None: + if if_data is None or if_data["depth"] != self.domain._depth: raise SyntaxError("Else without preceding If/Elif") try: _outer_case, self._statements = self._statements, [] diff --git a/tests/test_hdl_dsl.py b/tests/test_hdl_dsl.py index 6c5f117..a2d0c96 100644 --- a/tests/test_hdl_dsl.py +++ b/tests/test_hdl_dsl.py @@ -281,6 +281,34 @@ class DSLTestCase(FHDLTestCase): with m.Else(): pass + def test_Else_wrong_nested(self): + m = Module() + with m.If(self.s1): + with self.assertRaisesRegex(SyntaxError, + r"^Else without preceding If/Elif$"): + with m.Else(): + pass + + def test_Elif_Elif_wrong_nested(self): + m = Module() + with m.If(self.s1): + pass + with m.Elif(self.s2): + with self.assertRaisesRegex(SyntaxError, + r"^Elif without preceding If$"): + with m.Elif(self.s3): + pass + + def test_Else_Else_wrong_nested(self): + m = Module() + with m.If(self.s1): + pass + with m.Else(): + with self.assertRaisesRegex(SyntaxError, + r"^Else without preceding If/Elif$"): + with m.Else(): + pass + def test_If_wide(self): m = Module() with m.If(self.w1): -- 2.30.2