From 744a1a5af2fb9b128e4672dfb5b51e977aaea4f3 Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Wed, 21 Apr 2021 14:06:07 -0300 Subject: [PATCH] Fix sense of "invert" signal We want to put "1" in the mask, if the operation is to be performed. The actual CR bits are: LT, GT, EQ and SO. So, for those, we just copy the bit directly to the mask, as they are. For GE, LE, NE and NS, we want to invert the bit first. --- src/soc/simple/issuer.py | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index a5f7304f..66321857 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -124,28 +124,28 @@ def get_predcr(m, mask, name): with m.Switch(mask): with m.Case(SVP64PredCR.LT.value): comb += idx.eq(0) - comb += invert.eq(1) + comb += invert.eq(0) with m.Case(SVP64PredCR.GE.value): comb += idx.eq(0) - comb += invert.eq(0) + comb += invert.eq(1) with m.Case(SVP64PredCR.GT.value): comb += idx.eq(1) - comb += invert.eq(1) + comb += invert.eq(0) with m.Case(SVP64PredCR.LE.value): comb += idx.eq(1) - comb += invert.eq(0) + comb += invert.eq(1) with m.Case(SVP64PredCR.EQ.value): comb += idx.eq(2) - comb += invert.eq(1) + comb += invert.eq(0) with m.Case(SVP64PredCR.NE.value): comb += idx.eq(1) - comb += invert.eq(0) + comb += invert.eq(1) with m.Case(SVP64PredCR.SO.value): comb += idx.eq(3) - comb += invert.eq(1) + comb += invert.eq(0) with m.Case(SVP64PredCR.NS.value): comb += idx.eq(3) - comb += invert.eq(0) + comb += invert.eq(1) return idx, invert -- 2.30.2