From 744fc36ecedda983fd67019b9642a20454d33535 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Mon, 24 Apr 2023 20:38:35 -0700 Subject: [PATCH] Extended Mnemonics come *after* Special Registers Altered see addpcis in PowerISA v3.1B --- openpower/sv/rfc/ls013.mdwn | 39 +++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 19 deletions(-) diff --git a/openpower/sv/rfc/ls013.mdwn b/openpower/sv/rfc/ls013.mdwn index 4f7248915..218bb78b3 100644 --- a/openpower/sv/rfc/ls013.mdwn +++ b/openpower/sv/rfc/ls013.mdwn @@ -99,7 +99,7 @@ to 2019 there are now subtle differences. These are selectable with a Mode Field -| `FMM` | Assembly Alias | Origin | Semantics | +| `FMM` | Extended Mnemonic | Origin | Semantics | |-------|-------------------------------|--------------------------------|-------------------------------------------------| | 0000 | fminnum08[s] FRT, FRA, FRB | IEEE 754-2008 | FRT = minNum(FRA, FRB) (1) | | 0001 | fmin19[s] FRT, FRA, FRB | IEEE 754-2019 | FRT = minimum(FRA, FRB) | @@ -157,9 +157,6 @@ Note (3): TODO: icr if IEEE 754-2008 has min/maxMagNum like IEEE 754-2019's Compute the minimum/maximum of FRA and FRB, according to FMM, and store the result in FRT. -Assembly Aliases: see -[`FMM` -- Floating Min/Max Mode](#fmm-floating-min-max-mode) - Special Registers altered: ``` @@ -167,6 +164,10 @@ Special Registers altered: CR1 (if Rc=1) ``` +Extended Mnemonics: + +see [`FMM` -- Floating Min/Max Mode](#fmm-floating-min-max-mode) + ---------- ## Floating Minimum/Maximum Single MM-form @@ -182,9 +183,6 @@ Special Registers altered: Compute the minimum/maximum of FRA and FRB, according to FMM, and store the result in FRT. -Assembly Aliases: see -[`FMM` -- Floating Min/Max Mode](#fmm-floating-min-max-mode) - Special Registers altered: ``` @@ -192,7 +190,9 @@ Special Registers altered: CR1 (if Rc=1) ``` +Extended Mnemonics: +see [`FMM` -- Floating Min/Max Mode](#fmm-floating-min-max-mode) ---------- @@ -211,16 +211,16 @@ semantics therefore Saturated variants of these instructions need not be propose * bit 1: set if signed else unsigned * bit 2: set if max else min -| `MMM` | Assembly Alias | Semantics | -|-------|------------------|----------------------------------------------| -| 000 | `minu RT,RA,RB` | `RT = (uint64_t)RA < (uint64_t)RB ? RA : RB` | -| 001 | `maxu RT,RA,RB` | `RT = (uint64_t)RA > (uint64_t)RB ? RA : RB` | -| 010 | `mins RT,RA,RB` | `RT = (int64_t)RA < (int64_t)RB ? RA : RB` | -| 011 | `maxs RT,RA,RB` | `RT = (int64_t)RA > (int64_t)RB ? RA : RB` | -| 100 | `minuw RT,RA,RB` | `RT = (uint32_t)RA < (uint32_t)RB ? RA : RB` | -| 101 | `maxuw RT,RA,RB` | `RT = (uint32_t)RA > (uint32_t)RB ? RA : RB` | -| 110 | `minsw RT,RA,RB` | `RT = (int32_t)RA < (int32_t)RB ? RA : RB` | -| 111 | `maxsw RT,RA,RB` | `RT = (int32_t)RA > (int32_t)RB ? RA : RB` | +| `MMM` | Extended Mnemonic | Semantics | +|-------|-------------------|----------------------------------------------| +| 000 | `minu RT,RA,RB` | `RT = (uint64_t)RA < (uint64_t)RB ? RA : RB` | +| 001 | `maxu RT,RA,RB` | `RT = (uint64_t)RA > (uint64_t)RB ? RA : RB` | +| 010 | `mins RT,RA,RB` | `RT = (int64_t)RA < (int64_t)RB ? RA : RB` | +| 011 | `maxs RT,RA,RB` | `RT = (int64_t)RA > (int64_t)RB ? RA : RB` | +| 100 | `minuw RT,RA,RB` | `RT = (uint32_t)RA < (uint32_t)RB ? RA : RB` | +| 101 | `maxuw RT,RA,RB` | `RT = (uint32_t)RA > (uint32_t)RB ? RA : RB` | +| 110 | `minsw RT,RA,RB` | `RT = (int32_t)RA < (int32_t)RB ? RA : RB` | +| 111 | `maxsw RT,RA,RB` | `RT = (int32_t)RA > (int32_t)RB ? RA : RB` | ## Minimum/Maximum MM-Form @@ -273,8 +273,9 @@ Special Registers altered: CR0 (if Rc=1) ``` -Assembly Aliases: see -[`MMM` -- Integer Min/Max Mode](#mmm-integer-min-max-mode) +Extended Mnemonics: + +see [`MMM` -- Integer Min/Max Mode](#mmm-integer-min-max-mode) ---------- -- 2.30.2