From 74626185910fb5da623645539b44d7173382dcc2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 29 Apr 2015 19:55:32 +0200 Subject: [PATCH] Fixed memory_unpack for initialized memories --- passes/memory/memory_unpack.cc | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index e650facb4..0f8d5217f 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -76,6 +76,23 @@ void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) cell->setPort("\\DATA", memory->getPort("\\WR_DATA").extract(i*mem->width, mem->width)); } + Const initval = memory->parameters.at("\\INIT"); + for (int i = 0; i < GetSize(initval) && i/mem->width < (1 << abits); i += mem->width) { + Const val = initval.extract(i, mem->width, State::Sx); + for (auto bit : val.bits) + if (bit != State::Sx) + goto found_non_undef_initval; + continue; + found_non_undef_initval: + RTLIL::Cell *cell = module->addCell(NEW_ID, "$meminit"); + cell->parameters["\\MEMID"] = mem_name.str(); + cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS"); + cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH"); + cell->parameters["\\PRIORITY"] = i/mem->width; + cell->setPort("\\ADDR", SigSpec(i/mem->width, abits)); + cell->setPort("\\DATA", val); + } + module->remove(memory); } -- 2.30.2