From 74695162440687791b2ca370ba3c396db95da73a Mon Sep 17 00:00:00 2001 From: Bas Nieuwenhuizen Date: Sun, 30 Jun 2019 01:47:30 +0200 Subject: [PATCH] radv: Merge rsrc1/rsrc2 fields with the config fields. Reviewed-by: Samuel Pitoiset --- src/amd/vulkan/radv_pipeline.c | 36 ++++++++++++------------ src/amd/vulkan/radv_pipeline_cache.c | 5 ---- src/amd/vulkan/radv_shader.c | 42 ++++++++++++++-------------- src/amd/vulkan/radv_shader.h | 2 -- 4 files changed, 39 insertions(+), 46 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 49687405705..18235c4fe27 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2992,8 +2992,8 @@ radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs, radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4); radeon_emit(cs, va >> 8); radeon_emit(cs, S_00B124_MEM_BASE(va >> 40)); - radeon_emit(cs, shader->rsrc1); - radeon_emit(cs, shader->rsrc2); + radeon_emit(cs, shader->config.rsrc1); + radeon_emit(cs, shader->config.rsrc2); const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline); unsigned clip_dist_mask, cull_dist_mask, total_mask; @@ -3051,8 +3051,8 @@ radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs, radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4); radeon_emit(cs, va >> 8); radeon_emit(cs, S_00B324_MEM_BASE(va >> 40)); - radeon_emit(cs, shader->rsrc1); - radeon_emit(cs, shader->rsrc2); + radeon_emit(cs, shader->config.rsrc1); + radeon_emit(cs, shader->config.rsrc2); } static void @@ -3062,7 +3062,7 @@ radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs, const struct radv_tessellation_state *tess) { uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset; - uint32_t rsrc2 = shader->rsrc2; + uint32_t rsrc2 = shader->config.rsrc2; radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2); radeon_emit(cs, va >> 8); @@ -3074,7 +3074,7 @@ radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs, radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2); radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2); - radeon_emit(cs, shader->rsrc1); + radeon_emit(cs, shader->config.rsrc1); radeon_emit(cs, rsrc2); } @@ -3092,15 +3092,15 @@ radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs, radeon_emit(cs, S_00B414_MEM_BASE(va >> 40)); radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2); - radeon_emit(cs, shader->rsrc1); - radeon_emit(cs, shader->rsrc2 | + radeon_emit(cs, shader->config.rsrc1); + radeon_emit(cs, shader->config.rsrc2 | S_00B42C_LDS_SIZE_GFX9(tess->lds_size)); } else { radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4); radeon_emit(cs, va >> 8); radeon_emit(cs, S_00B424_MEM_BASE(va >> 40)); - radeon_emit(cs, shader->rsrc1); - radeon_emit(cs, shader->rsrc2); + radeon_emit(cs, shader->config.rsrc1); + radeon_emit(cs, shader->config.rsrc2); } } @@ -3218,8 +3218,8 @@ radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs, radeon_emit(cs, S_00B214_MEM_BASE(va >> 40)); radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2); - radeon_emit(cs, gs->rsrc1); - radeon_emit(cs, gs->rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size)); + radeon_emit(cs, gs->config.rsrc1); + radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size)); radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl); radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup); @@ -3227,8 +3227,8 @@ radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs, radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4); radeon_emit(cs, va >> 8); radeon_emit(cs, S_00B224_MEM_BASE(va >> 40)); - radeon_emit(cs, gs->rsrc1); - radeon_emit(cs, gs->rsrc2); + radeon_emit(cs, gs->config.rsrc1); + radeon_emit(cs, gs->config.rsrc2); } radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader); @@ -3384,8 +3384,8 @@ radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs, radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4); radeon_emit(cs, va >> 8); radeon_emit(cs, S_00B024_MEM_BASE(va >> 40)); - radeon_emit(cs, ps->rsrc1); - radeon_emit(cs, ps->rsrc2); + radeon_emit(cs, ps->config.rsrc1); + radeon_emit(cs, ps->config.rsrc2); radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL, radv_compute_db_shader_control(pipeline->device, @@ -3903,8 +3903,8 @@ radv_compute_generate_pm4(struct radv_pipeline *pipeline) radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40)); radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2); - radeon_emit(&pipeline->cs, compute_shader->rsrc1); - radeon_emit(&pipeline->cs, compute_shader->rsrc2); + radeon_emit(&pipeline->cs, compute_shader->config.rsrc1); + radeon_emit(&pipeline->cs, compute_shader->config.rsrc2); radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE, S_00B860_WAVES(pipeline->max_waves) | diff --git a/src/amd/vulkan/radv_pipeline_cache.c b/src/amd/vulkan/radv_pipeline_cache.c index 57d52610306..a506711898a 100644 --- a/src/amd/vulkan/radv_pipeline_cache.c +++ b/src/amd/vulkan/radv_pipeline_cache.c @@ -34,7 +34,6 @@ struct cache_entry_variant_info { struct radv_shader_variant_info variant_info; struct ac_shader_config config; - uint32_t rsrc1, rsrc2; }; struct cache_entry { @@ -324,8 +323,6 @@ radv_create_shader_variants_from_pipeline_cache(struct radv_device *device, variant->config = info.config; variant->info = info.variant_info; - variant->rsrc1 = info.rsrc1; - variant->rsrc2 = info.rsrc2; variant->code_size = entry->code_sizes[i]; variant->ref_count = 1; @@ -413,8 +410,6 @@ radv_pipeline_cache_insert_shaders(struct radv_device *device, info.config = variants[i]->config; info.variant_info = variants[i]->info; - info.rsrc1 = variants[i]->rsrc1; - info.rsrc2 = variants[i]->rsrc2; memcpy(p, &info, sizeof(struct cache_entry_variant_info)); p += sizeof(struct cache_entry_variant_info); diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index a07c10a9808..3d71ab73288 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -481,19 +481,19 @@ radv_fill_shader_variant(struct radv_device *device, unsigned vgpr_comp_cnt = 0; variant->code_size = radv_get_shader_binary_size(binary); - variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) | - S_00B12C_USER_SGPR_MSB_GFX9(variant->info.num_user_sgprs >> 5) | - S_00B12C_SCRATCH_EN(scratch_enabled) | - S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) | - S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) | - S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) | - S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) | - S_00B12C_SO_EN(!!info->so.num_outputs); - - variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) | - S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) | - S_00B848_DX10_CLAMP(1) | - S_00B848_FLOAT_MODE(variant->config.float_mode); + variant->config.rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) | + S_00B12C_USER_SGPR_MSB_GFX9(variant->info.num_user_sgprs >> 5) | + S_00B12C_SCRATCH_EN(scratch_enabled) | + S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) | + S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) | + S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) | + S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) | + S_00B12C_SO_EN(!!info->so.num_outputs); + + variant->config.rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) | + S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) | + S_00B848_DX10_CLAMP(1) | + S_00B848_FLOAT_MODE(variant->config.float_mode); switch (stage) { case MESA_SHADER_TESS_EVAL: @@ -504,7 +504,7 @@ radv_fill_shader_variant(struct radv_device *device, bool enable_prim_id = options->key.tes.export_prim_id || info->uses_prim_id; vgpr_comp_cnt = enable_prim_id ? 3 : 2; } - variant->rsrc2 |= S_00B12C_OC_LDS_EN(1); + variant->config.rsrc2 |= S_00B12C_OC_LDS_EN(1); break; case MESA_SHADER_TESS_CTRL: if (device->physical_device->rad_info.chip_class >= GFX9) { @@ -514,7 +514,7 @@ radv_fill_shader_variant(struct radv_device *device, */ vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1; } else { - variant->rsrc2 |= S_00B12C_OC_LDS_EN(1); + variant->config.rsrc2 |= S_00B12C_OC_LDS_EN(1); } break; case MESA_SHADER_VERTEX: @@ -547,7 +547,7 @@ radv_fill_shader_variant(struct radv_device *device, case MESA_SHADER_GEOMETRY: break; case MESA_SHADER_COMPUTE: - variant->rsrc2 |= + variant->config.rsrc2 |= S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) | S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) | S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) | @@ -588,14 +588,14 @@ radv_fill_shader_variant(struct radv_device *device, gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */ } - variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt); - variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) | - S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL); + variant->config.rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt); + variant->config.rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) | + S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL); } else if (device->physical_device->rad_info.chip_class >= GFX9 && stage == MESA_SHADER_TESS_CTRL) { - variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt); + variant->config.rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt); } else { - variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt); + variant->config.rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt); } void *ptr = radv_alloc_shader_memory(device, variant); diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index d3d8a2dd37b..f6f345e1eed 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -314,8 +314,6 @@ struct radv_shader_variant { struct ac_shader_config config; uint32_t code_size; struct radv_shader_variant_info info; - unsigned rsrc1; - unsigned rsrc2; /* debug only */ uint32_t *spirv; -- 2.30.2