From 746fc346eae21d227b06799f3e82a1404c75bdc9 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Mon, 26 Nov 2012 23:52:20 -0800 Subject: [PATCH] i965/vs: Rework memory contexts for shader compilation data. During compilation, we allocate a bunch of things: the IR needs to last at least until code generation...and then the program store needs to last until after we upload the program. For simplicity's sake, just keep it all around until we upload the program. After that, it can all be freed. This will also save a lot of headaches during the upcoming refactoring. Reviewed-by: Eric Anholt Reviewed-by: Anuj Phogat --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 5 +++-- src/mesa/drivers/dri/i965/brw_vec4.h | 4 +++- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 6 +++--- src/mesa/drivers/dri/i965/brw_vs.c | 2 +- src/mesa/drivers/dri/i965/brw_vs.h | 3 ++- 5 files changed, 12 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index d203ca90765..7e6e79e5e7e 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp @@ -1130,7 +1130,8 @@ extern "C" { bool brw_vs_emit(struct brw_context *brw, struct gl_shader_program *prog, - struct brw_vs_compile *c) + struct brw_vs_compile *c, + void *mem_ctx) { struct intel_context *intel = &brw->intel; bool start_busy = false; @@ -1169,7 +1170,7 @@ brw_vs_emit(struct brw_context *brw, shader->compiled_once = true; } - vec4_visitor v(brw, c, prog, shader); + vec4_visitor v(brw, c, prog, shader, mem_ctx); if (!v.run()) { prog->LinkStatus = false; ralloc_strcat(&prog->InfoLog, v.fail_msg); diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h index f474b0f7621..3d9d0dc504f 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.h +++ b/src/mesa/drivers/dri/i965/brw_vec4.h @@ -200,7 +200,9 @@ class vec4_visitor : public backend_visitor public: vec4_visitor(struct brw_context *brw, struct brw_vs_compile *c, - struct gl_shader_program *prog, struct brw_shader *shader); + struct gl_shader_program *prog, + struct brw_shader *shader, + void *mem_ctx); ~vec4_visitor(); dst_reg dst_null_f() diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index 982b74c19ec..4579e0c45e7 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp @@ -2809,7 +2809,8 @@ vec4_visitor::resolve_ud_negate(src_reg *reg) vec4_visitor::vec4_visitor(struct brw_context *brw, struct brw_vs_compile *c, struct gl_shader_program *prog, - struct brw_shader *shader) + struct brw_shader *shader, + void *mem_ctx) { this->c = c; this->p = &c->func; @@ -2819,7 +2820,7 @@ vec4_visitor::vec4_visitor(struct brw_context *brw, this->prog = prog; this->shader = shader; - this->mem_ctx = ralloc_context(NULL); + this->mem_ctx = mem_ctx; this->failed = false; this->base_ir = NULL; @@ -2849,7 +2850,6 @@ vec4_visitor::vec4_visitor(struct brw_context *brw, vec4_visitor::~vec4_visitor() { - ralloc_free(this->mem_ctx); hash_table_dtor(this->variable_ht); } diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c index ff91f4eadc0..b1b7a4f35a5 100644 --- a/src/mesa/drivers/dri/i965/brw_vs.c +++ b/src/mesa/drivers/dri/i965/brw_vs.c @@ -279,7 +279,7 @@ do_vs_prog(struct brw_context *brw, /* Emit GEN4 code. */ - if (!brw_vs_emit(brw, prog, &c)) { + if (!brw_vs_emit(brw, prog, &c, mem_ctx)) { ralloc_free(mem_ctx); return false; } diff --git a/src/mesa/drivers/dri/i965/brw_vs.h b/src/mesa/drivers/dri/i965/brw_vs.h index 2c085474733..d0e260e4e81 100644 --- a/src/mesa/drivers/dri/i965/brw_vs.h +++ b/src/mesa/drivers/dri/i965/brw_vs.h @@ -105,7 +105,8 @@ struct brw_vs_compile { bool brw_vs_emit(struct brw_context *brw, struct gl_shader_program *prog, - struct brw_vs_compile *c); + struct brw_vs_compile *c, + void *mem_ctx); bool brw_vs_precompile(struct gl_context *ctx, struct gl_shader_program *prog); void brw_vs_debug_recompile(struct brw_context *brw, struct gl_shader_program *prog, -- 2.30.2