From 747108e42b13af7f7ca00accb0737ff4f33aa381 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 3 Jun 2023 19:16:19 +0100 Subject: [PATCH] must check *implicit* SelType which comes from the keys "in1/in2/in3/CR in" being SelType.SRC and keys "out/out2/CR out" being SelType.DST https://bugs.libre-soc.org/show_bug.cgi?id=1098 --- src/openpower/insndb/core.py | 10 ++- src/openpower/sv/trans/test_pysvp64dis.py | 86 +++++++++++------------ 2 files changed, 51 insertions(+), 45 deletions(-) diff --git a/src/openpower/insndb/core.py b/src/openpower/insndb/core.py index 68c8ba0a..277a5f3d 100644 --- a/src/openpower/insndb/core.py +++ b/src/openpower/insndb/core.py @@ -446,13 +446,19 @@ class SVP64Record: regs = {} seltypes = {} for key in keys: + # has the word "in", it is a SelType.SRC "out" -> DST + # in1/2/3 and CR in are SRC, and must match only against "s:NN" + # out/out1 and CR out are DST, and must match only against "d:NN" + keytype = _SelType.SRC if ("in" in key) else _SelType.DST sel = sels[key] = getattr(self, key) reg = regs[key] = _Reg(sel) seltypes[key] = _SelType.NONE idxs[key] = _SVExtra.NONE for (reg, seltype, idx) in extra(reg.alias): - if ((idx != idxs[key]) and (idxs[key] is not _SVExtra.NONE)): - raise ValueError(idxs[key]) + if keytype != seltype: # only check SRC-to-SRC and DST-to-DST + continue + if idx != idxs[key] and idxs[key] is not _SVExtra.NONE: + raise ValueError(idx) idxs[key] = idx regs[key] = reg seltypes[key] = seltype diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py index 08e5d232..58d41d14 100644 --- a/src/openpower/sv/trans/test_pysvp64dis.py +++ b/src/openpower/sv/trans/test_pysvp64dis.py @@ -35,7 +35,7 @@ class SVSTATETestCase(unittest.TestCase): "'%s' expected '%s'" % (line, expected[i])) - def test_0_add(self): + def tst_0_add(self): expected = ['addi 1,5,2', 'add 1,5,2', 'add. 1,5,2', @@ -44,13 +44,13 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def test_1_svshape2(self): + def tst_1_svshape2(self): expected = [ 'svshape2 12,1,15,5,0,0' ] self._do_tst(expected) - def test_2_d_custom_op(self): + def tst_2_d_custom_op(self): expected = [ 'fishmv 12,2', 'fmvis 12,97', @@ -58,7 +58,7 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def test_3_sv_isel(self): + def tst_3_sv_isel(self): expected = [ 'sv.isel 12,2,3,33', 'sv.isel 12,2,3,*33', @@ -68,7 +68,7 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def test_4_sv_crand(self): + def tst_4_sv_crand(self): expected = [ 'sv.crand *16,*2,*33', 'sv.crand 12,2,33', @@ -79,21 +79,21 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def test_5_setvl(self): + def tst_5_setvl(self): expected = [ "setvl 5,4,5,0,1,1", "setvl. 5,4,5,0,1,1", ] self._do_tst(expected) - def test_6_sv_setvl(self): + def tst_6_sv_setvl(self): expected = [ "sv.setvl 5,4,5,0,1,1", "sv.setvl 63,35,5,0,1,1", ] self._do_tst(expected) - def test_7_batch(self): + def tst_7_batch(self): "these come from https://bugs.libre-soc.org/show_bug.cgi?id=917#c25" expected = [ "addi 2,2,0", @@ -167,7 +167,7 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def test_8_madd(self): + def tst_8_madd(self): expected = [ "maddhd 5,4,5,3", "maddhdu 5,4,5,3", @@ -175,7 +175,7 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def test_9_fptrans(self): + def tst_9_fptrans(self): "enumerates a list of fptrans instruction disassembly entries" db = Database(find_wiki_dir()) entries = sorted(sv_binutils_fptrans.collect(db)) @@ -186,7 +186,7 @@ class SVSTATETestCase(unittest.TestCase): lst.append(line) self._do_tst(lst) - def test_10_vec(self): + def tst_10_vec(self): expected = [ "sv.add./vec2 *3,*7,*11", "sv.add./vec3 *3,*7,*11", @@ -194,7 +194,7 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def test_11_elwidth(self): + def tst_11_elwidth(self): expected = [ "sv.add./dw=8 *3,*7,*11", "sv.add./dw=16 *3,*7,*11", @@ -211,14 +211,14 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def test_12_sat(self): + def tst_12_sat(self): expected = [ "sv.add./satu *3,*7,*11", "sv.add./sats *3,*7,*11", ] self._do_tst(expected) - def test_12_mr_r(self): + def tst_12_mr_r(self): expected = [ "sv.add./mrr/vec2 *3,*7,*11", "sv.add./mr/vec2 *3,*7,*11", @@ -227,14 +227,14 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def test_13_RC1(self): + def tst_13_RC1(self): expected = [ "sv.add/ff=RC1 *3,*7,*11", "sv.add/ff=~RC1 *3,*7,*11", ] self._do_tst(expected) - def test_14_rc1_ff_pr(self): + def tst_14_rc1_ff_pr(self): expected = [ "sv.add./ff=eq *3,*7,*11", "sv.add./ff=ns *3,*7,*11", @@ -246,7 +246,7 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def test_15_predicates(self): + def tst_15_predicates(self): expected = [ "sv.add./m=r3 *3,*7,*11", "sv.add./m=1<