From 74810fd6867e426d638dc34a2f97e627b530b40e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 26 Jun 2022 09:46:32 +0100 Subject: [PATCH] svp64_matrix.py svremap reduce to 7 args from 8 (again) --- src/openpower/decoder/isa/test_caller_svp64_matrix.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py index c15479db..130f9472 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py +++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py @@ -93,13 +93,13 @@ class DecoderTestCase(FHDLTestCase): def test_sv_remap2(self): """>>> lst = ["svshape 5, 4, 3, 0, 0", - "svremap 31, 1, 2, 3, 0, 0, 0, 0", + "svremap 31, 1, 2, 3, 0, 0, 0", "sv.fmadds 0.v, 8.v, 16.v, 0.v" ] REMAP fmadds FRT, FRA, FRC, FRB """ lst = SVP64Asm(["svshape 4, 3, 3, 0, 0", - "svremap 31, 1, 2, 3, 0, 0, 0, 0", + "svremap 31, 1, 2, 3, 0, 0, 0", "sv.fmadds 0.v, 16.v, 32.v, 0.v" ]) lst = list(lst) -- 2.30.2