From 74a26d27c5aa6ab687668234f5a2e38f7527bcc2 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 13 Dec 2020 23:52:52 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index 87e084e9a..758296263 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -218,7 +218,7 @@ standard vector instruction with Rc=1. # Register Profiles Instructions are broken down by Register Profiles as listed in the following auto-generated page: -[[opcode_regs_deduped]]. "Non-SV" indicates that the operations with this Register Profile cannot be Vectorised (dcbz, twi) +[[opcode_regs_deduped]]. "Non-SV" indicates that the operations with this Register Profile cannot be Vectorised (mtspr, bc, dcbz, twi) ## LDST-1R-1W-imm TBD @@ -239,7 +239,7 @@ TBD ## LDST-3R-1W TBD ## CRi -TBD +non-SV ## CRio TBD ## CR=2R1W -- 2.30.2