From 74af2211e60d3e4fdf6f0016a85a62b6a40f88f8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 5 May 2020 15:48:14 +0100 Subject: [PATCH] allow rtlil file to be created in cordic --- src/ieee754/cordic/test/test_fp_pipe.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/ieee754/cordic/test/test_fp_pipe.py b/src/ieee754/cordic/test/test_fp_pipe.py index 698efc95..56f853c7 100644 --- a/src/ieee754/cordic/test/test_fp_pipe.py +++ b/src/ieee754/cordic/test/test_fp_pipe.py @@ -17,10 +17,10 @@ class SinCosTestCase(FHDLTestCase): pspec = FPCordicPipeSpec(width=32, rounds_per_stage=4, num_rows=1) m.submodules.dut = dut = FPCordicBasePipe(pspec) - - # vl = rtlil.convert(dut, ports=dut.ports()) - # with open("test_cordic_pipe_sin_cos.il", "w") as f: - # f.write(vl) + # write out module (useful for seeing what's going on) + vl = rtlil.convert(dut, ports=dut.ports()) + with open("test_cordic_pipe_sin_cos.il", "w") as f: + f.write(vl) z = Signal(dut.p.data_i.a.shape()) z_valid = Signal() -- 2.30.2