From 74b4b03c6ffb028770cf7bbfa4229ea481e3aff0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 12 Apr 2021 14:06:53 +0000 Subject: [PATCH] update PLL signal output names --- experiments9/tsmc_c018/doDesign.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/experiments9/tsmc_c018/doDesign.py b/experiments9/tsmc_c018/doDesign.py index 041d80b..fdc3bdd 100644 --- a/experiments9/tsmc_c018/doDesign.py +++ b/experiments9/tsmc_c018/doDesign.py @@ -195,9 +195,13 @@ def scriptMain (**kw): , (IoPin.SOUTH, None, 'sys_rst', 'sys_rst', 'sys_rst' ) ] ioPadsSpec += doIoPinVector( (IoPin.SOUTH, None, 'nc_{}', 'nc({})', 'nc({})'), range(23,24) ) - ioPadsSpec += [ (IoPin.SOUTH, None, 'sys_pll_18_o' , 'sys_pll_18_o' , 'sys_pll_18_o' ) ] + # TODO, Jean-Paul, resolve these + # this one is analog voltage out (test purposes) vco_test_ana + ioPadsSpec += [ (IoPin.SOUTH, None, 'sys_pll_vco_o' , 'sys_pll_vco_o' , 'sys_pll_vco_o' ) ] + # this one is the divided internal PLL clock, div_out_test + ioPadsSpec += [ (IoPin.SOUTH, None, 'sys_pll_testout_o' , 'sys_pll_testout_o' , 'sys_pll_testout_o' ) ] + # these are a0, a1 in the PLL block, for selecting the PLL clock rate out ioPadsSpec += doIoPinVector( (IoPin.SOUTH, None, 'sys_clksel_i{}', 'sys_clksel_i({})', 'sys_clksel_i({})'), 2 ) - ioPadsSpec += [ (IoPin.SOUTH, None, 'sys_pll_lck_o' , 'sys_pll_lck_o' , 'sys_pll_lck_o' ) ] ioPadsSpec += doIoPowerCap( IoPin.SOUTH|IoPin.A_END ) try: cell, editor = plugins.kwParseMain( **kw ) -- 2.30.2