From 74bd190d3bb3d606f95e9c565ca8ccec70fca290 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 22 Aug 2019 11:14:59 -0700
Subject: [PATCH] Remove output_bits

---
 passes/pmgen/xilinx_srl.cc  | 13 +------------
 passes/pmgen/xilinx_srl.pmg | 10 ++++++----
 2 files changed, 7 insertions(+), 16 deletions(-)

diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc
index d1dbd77ae..0120a6c2c 100644
--- a/passes/pmgen/xilinx_srl.cc
+++ b/passes/pmgen/xilinx_srl.cc
@@ -214,19 +214,8 @@ struct XilinxSrlPass : public Pass {
 				pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_R_INVERTED))] = State::S0;
 				pm.run_fixed(run_fixed);
 			}
-			if (variable) {
-				// Since `nusers` does not count module ports as a user,
-				//   and since `sigmap` does not always make such ports
-				//   the canonical signal.. need to maintain a pool these
-				//   ourselves
-				for (auto p : module->ports) {
-					auto w = module->wire(p);
-					if (w->port_output)
-						for (auto b : pm.sigmap(w))
-							pm.ud_variable.output_bits.insert(b);
-				}
+			if (variable)
 				pm.run_variable(run_variable);
-			}
 		}
 	}
 } XilinxSrlPass;
diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg
index 4558234de..0cc551e92 100644
--- a/passes/pmgen/xilinx_srl.pmg
+++ b/passes/pmgen/xilinx_srl.pmg
@@ -152,13 +152,12 @@ pattern variable
 
 state <int> shiftx_width
 udata <int> minlen
-udata <pool<SigBit>> output_bits
 udata <vector<Cell*>> chain
 
 match shiftx
 	select shiftx->type.in($shiftx)
 	select !shiftx->has_keep_attr()
-	select param(shiftx, \Y_WIDTH) == 1
+	select param(shiftx, \Y_WIDTH).as_int() == 1
 	filter param(shiftx, \A_WIDTH).as_int() >= minlen
 endmatch
 
@@ -170,7 +169,6 @@ match first
 	select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_)
 	select nusers(port(first, \Q)) == 2
 	index <SigBit> port(first, \Q) === port(shiftx, \A)[shiftx_width-1]
-	filter !output_bits.count(port(first, \Q))
 endmatch
 
 code
@@ -194,7 +192,6 @@ match next
 	select !next->has_keep_attr()
 	select !port(next, \D)[0].wire->get_bool_attribute(\keep)
 	select nusers(port(next, \Q)) == 3
-	filter !output_bits.count(port(next, \Q))
 	index <IdString> next->type === chain.back()->type
 	index <SigBit> port(next, \Q) === port(chain.back(), \D)
 	index <SigBit> port(next, \Q) === port(shiftx, \A)[shiftx_width-1-GetSize(chain)]
@@ -202,6 +199,11 @@ endmatch
 
 code
 	if (next) {
+		auto sig = port(next, \Q);
+		log_warning("nusers of '%s'\n", log_signal(sig));
+		for (auto bit : sigmap(sig))
+			for (auto user : sigusers[bit])
+				log_warning("\t%s\n", log_id(user));
 		chain.push_back(next);
 		if (GetSize(chain) < shiftx_width)
 			subpattern(tail);
-- 
2.30.2