From 74c804790f498eb6c96b8c20cd16224fe98e5409 Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 4 Jul 2022 11:47:54 +0100 Subject: [PATCH] --- openpower/sv/setvl.mdwn | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn index dcbfec2e5..df6002356 100644 --- a/openpower/sv/setvl.mdwn +++ b/openpower/sv/setvl.mdwn @@ -101,8 +101,9 @@ i.e. that an immediate value of 1 in assembler notation actually places the value 0b0000000 in the `SVi` field bits: on execution the `setvl` instruction adds one to the decoded `SVi` field bits, resulting in -VL/MVL being set to 1. This is because setting -VL/MVL to 1 results in "scalar identity" behaviour, where setting VL/MVL +VL/MVL being set to 1. This allows VL to be set to values +ranging from 1 to 128 with only 7 bits instead of 8. +Setting VL/MVL to 0 would result in all Vector operations becoming `nop`. If this is truly desired (nop behaviour) then setting VL and MVL to zero is to be done via the [[SVSTATE SPR|sv/sprs]]. -- 2.30.2