From 74d5a6acffcf3f8d1f090f6002d075d6a95c5390 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 5 May 2022 23:13:24 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index ecce194ee..60e865b96 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -305,4 +305,13 @@ Remarkably, very little: the devil is in the details though. It is only when looking slightly deeper into the Power ISA that certain things turn out to be missing, and this is down in part to IBM's primary focus on the 750 Packed SIMD opcodes at the expense of the 250 or -so Scalar ones. +so Scalar ones. Examples include that transfer operations between the +Integer and Floating-point Scalar register files were dropped approximately +a decade ago after the Packed SIMD variants were considered to be +duplicates. With it being completely inappropriate to attempt to Vectorise +a Packed SIMD ISA designed 20 years ago with no Predication of any kind, +the Scalar ISA, a much better all-round candidate for Vectorisation is +left anaemic. Fortunately, with the ISA Working Group being willing +to consider RFCs (Requests For Change) these omissions have the potential +to be corrected. + -- 2.30.2