From 74d9ea3eef80236bbbf03b8d7a1e9114da567783 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 18 Jun 2022 22:48:59 +0100
Subject: [PATCH] move para

---
 openpower/sv.mdwn | 36 ++++++++++++++++++++----------------
 1 file changed, 20 insertions(+), 16 deletions(-)

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 4343cf76f..25a114de5 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -175,6 +175,26 @@ Additional links:
 * [[simple_v_extension]] old (deprecated) version
 * [[openpower/sv/llvm]]
 
+# Other Scalable Vector ISAs
+
+* Original Cray ISA
+  <http://www.bitsavers.org/pdf/cray/CRAY_Y-MP/HR-04001-0C_Cray_Y-MP_Computer_Systems_Functional_Description_Jun90.pdf>
+* NEC SX Aurora (still in production, inspired by Cray)
+  <https://www.hpc.nec/documents/guide/pdfs/Aurora_ISA_guide.pdf>
+* RISC-V RVV (inspired by Cray)
+  <https://github.com/riscv/riscv-v-spec>
+* MRISC32 ISA Manual (under active development)
+  <https://github.com/mrisc32/mrisc32/tree/master/isa-manual>
+* Mitch Alsup's MyISA 66000 Vector Processor ISA Manual is available from
+  Mitch on request.
+
+A comprehensive list of 3D GPU, Packed SIMD, Predicated-SIMD and true Scalable
+Vector ISAs may be found at the [[sv/vector_isa_comparison]] page.
+Note: AVX-512 and SVE2 are *not strict Vector ISAs*, they are Predicated-SIMD.
+*Public discussions have taken place at Conferences attended by both Intel
+and ARM on adding a `setvl` instruction which would easily make both
+AVX-512 and SVE2 truly "Scalable".*
+
 # Major opcodes summary
 
 Simple-V itself only requires four instructions with 6-bit Minor XO
@@ -237,19 +257,3 @@ the heavy focus on VSX for the past 12 years has left the SFFS Level
 anaemic and out-of-date compared to ARM and x86. Approximately
 100 additional Scalar Instructions are up for proposal**
 
-# Other Scalable Vector ISAs
-
-* Original Cray ISA
-  <http://www.bitsavers.org/pdf/cray/CRAY_Y-MP/HR-04001-0C_Cray_Y-MP_Computer_Systems_Functional_Description_Jun90.pdf>
-* NEC SX Aurora (still in production, inspired by Cray)
-  <https://www.hpc.nec/documents/guide/pdfs/Aurora_ISA_guide.pdf>
-* RISC-V RVV (inspired by Cray)
-  <https://github.com/riscv/riscv-v-spec>
-* MRISC32 ISA Manual (under active development)
-  <https://github.com/mrisc32/mrisc32/tree/master/isa-manual>
-* Mitch Alsup's MyISA 66000 Vector Processor ISA Manual is available from
-  Mitch on request.
-
-A comprehensive list of 3D GPU, Packed SIMD, Predicated-SIMD and true Scalable
-Vector ISAs may be found at the [[sv/vector_isa_comparison]] page.
-Note: AVX-512 and SVE2 are *not strict Vector ISAs*, they are Predicated-SIMD.
-- 
2.30.2