From 74e74dc0e7c6a258ad4a1104c3d1a11a78159601 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 25 Sep 2018 09:09:47 +0200 Subject: [PATCH] soc/cores/clock: different clkin_freq_range for pll and mmcm --- litex/soc/cores/clock.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py index d576c0c6..518a94af 100644 --- a/litex/soc/cores/clock.py +++ b/litex/soc/cores/clock.py @@ -15,7 +15,6 @@ def period_ns(freq): class S7Clocking(Module): - clkin_freq_range = (10e6, 800e6) clkfbout_mult_frange = (2, 64+1) clkout_divide_range = (1, 128+1) @@ -91,6 +90,7 @@ class S7Clocking(Module): class S7PLL(S7Clocking): nclkouts_max = 6 + clkin_freq_range = (19e6, 800e6) def __init__(self, speedgrade=-1): S7Clocking.__init__(self) @@ -124,6 +124,12 @@ class S7MMCM(S7Clocking): def __init__(self, speedgrade=-1): S7Clocking.__init__(self) + self.clkin_freq_range = { + -1: (10e6, 800e6), + -2: (10e6, 933e6), + -3: (10e6, 1066e6), + }[speedgrade] + self.vco_freq_range = { -1: (600e6, 1200e6), -2: (600e6, 1440e6), -- 2.30.2