From 74ea4381362d4f402e7fc262b960e14122128303 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 22 Nov 2019 16:52:55 -0800 Subject: [PATCH] Add testcase for signal used as part input part output --- tests/simple_abc9/abc9.v | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 6bdd3bc32..8314af211 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -289,3 +289,8 @@ module abc9_test033(input clk, d, output reg q1, q2); always @(posedge clk) q1 <= d; always @(posedge clk) q2 <= q1; endmodule + +module abc9_test034(input clk, d, output reg [1:0] q); +always @(posedge clk) q[0] <= d; +always @(negedge clk) q[1] <= q[0]; +endmodule -- 2.30.2